Circuit Design Problems Research Articles

A BDD SAT solver for satisfiability testing: An industrial case study

The satisfiability problem (SAT) is a fundamental problem in mathematical logic, constraint satisfaction, VLSI engineering, and computing theory. Methods to solve the satisfiability problem play an important role in the development of computing theory and systems. In this paper, we give a BDD (Binary Decision Diagrams) SAT solver for practical asynchronous circuit design. The BDD SAT solver consists of a structural SAT formula preprocessor and a complete, incremental SAT algorithm that is able to find an optimal solution. The preprocessor compresses a large size SAT formula representing the circuit into a number of smaller SAT formulas. This avoids the problem of solving very large SAT formulas. Each small size SAT formula is solved by the BDD SAT algorithm efficiently. Eventually, the results of these subproblems are integrated together that contribute to the solution of the original problem. According to recent industrial assessments, this BDD SAT solver provides solutions to the practical, industrial asynchronous circuit design problems.

Generalized formulation of yield, variability, minimax and Taguchi circuit optimization problems

A generalized formulation of several circuit design problems, such as manufacturing yield optimization, circuit performance variability minimization, deterministic and statistical minimax design, Income Index maximization, Taguchi approach, etc., is developed. Several other “intermediate” problems can be defined in a sense similar to the one used in Zadeh's fuzzy set theory. A specific problem is identified by the selection of a generalized membership function ω(·) of the acceptability region, and a sequence of the values of the “smoothing” parameter β. Generalized gradient formulas are developed, and various possible algorithmic implementations discussed. As a result, trade-offs between different design strategies can be investigated by circuit designers, within one coherent methodology.

Low-noise electronic system design

From the Publisher: Emphasizes IC design concepts with additional support for discrete design where necessary. Describes noise sources and models; addresses practical problems of circuit design for low noise using negative feedback, filtering, component noise, measurement techniques and instrumentation; gives numerous examples of practical amplifier designs. Five chapters cover the use of SPICE and PSpice for low noise analysis and design.

Multiple-criteria robust design of electronic devices

Developed in Japan and becoming increasingly talked about under the name 'Taguchi methods', robust design minimizes the sensitivity of a product or a process to external uncontrolled factors. The present paper expands robust design methods to situations common in electronics design in which design factors interact or in which multiple performance characteristics are to be made robust. This paper proposes a constrained optimization method to achieve robust performance of electronic devices, by limiting attention to only the truly relevant (i.e. feasible) designs that meet all target performance criteria. A recently-solved circuit design problem is revisited to illustrate the proposed method's superior model development, optimization, and robustness-seeking capability.

Experiments using interval analysis for solving a circuit design problem

An already classical attempt at solving a circuit design problem leads to a system of 9 nonlinear equations in 9 variables. The sensitivity of the problem to small perturbations is extraordinarily high. Since 1974 several investigations have been made into this problem and they hint at one solution in the restricted domain of the nonnegative reals. The investigations did not give error estimates nor did they present conclusive evidence that the solution found is the only one in the domain of the nonnegative reals. Our paper reports on experimental computations which used various kinds of interval analytic methods while also sometimes reflecting on Wright-Cutteridge's philosophy and theses. The computations resulted in a guarantee that in the domain of consideration, that is, the interval [0,10] for each of the 9 variables, exactly one solution did exist, which was near the solution known up to now. Finally, our solution could be localized within a parallelpiped with edge lengths between 10−6 and 3.2-10−4.

Monotonicity Analysis of Taguchi’s Robust Circuit Design Problem

Taguchi’s robust circuit design problem can be formulated rigorously as an optimization problem. A necessary condition for optimality is that the control range be centered about the target value. This generates a constraint on the two design variables which cannot be solved for either variable. The present article shows that by approximating this unsolvable constraint with a simpler constraint that is solvable, one variable can be eliminated and the problem reduced to an unconstrained one in a single variable. Since this reduced objective turns out to be monotonic in the remaining design variable, its optimum value must be at the limit of its range. The corresponding optimum value of the other variable is then determined exactly from the true, not approximate, constraint. Since no model construction, experimentation, statistical analysis, or numerical iteration is needed, this procedure is recommended whenever the input-output relation is known to be a monotonic algebraic function.

Synthesis tools help teach systems concepts in VLSI design

The VLSI project class at Princeton University has been redesigned, using modern logic and layout synthesis tools, to emphasize system design issues. The design methodology taught in the class allows students to build larger designs; it also allows them to learn, by redesign, how to trade off layout, circuit, logic, and architectural design problems. Two synthesis tools were developed (based on the Oct tool set from UC Berkeley) to generate standard cell layouts: one which takes as input finite-state machine transition tables; and one which generates netlists using C programs. The author describes; what is important for students to learn in a VLSI design class; the design methodology developed to teach this curriculum through a design project; and the CAD tools used to support this design methodology.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Interaction between process design and process control: the role of open-loop indicators

Abstract The role of various open-loop indicators of inherent process controllability in assessing alternative flow-sheets is investigated. Eleven alternative flowsheets for a flotation circuit design problem were each optimized so as to maximize recovery of a valuable mineral in the feed. The following open-loop indicators were also determined for each flowsheet — two condition numbers; the minimum singular value; an interaction angle measure 1 and right half plane zeros. These indicators divided the flowsheets into a ‘good’, inherently easy to control, group and a ‘bad’ group. For a given flowsheet the various open-loop indicators were consistent in their predictions as to ease of control. The controllability rankings based on the open-loop indicators (all developed from linearized models) were confirmed by the results of nonlinear closed-loop dynamic simulations. The flowsheet with the highest steady-state recovery (i.e. potentially the most porfitable) was shown to be the least controllable, highlighting the need for process operability to be an integral part of the design process.

Causal model progressions as a foundation for intelligent learning environments

AI research in qualitative modeling makes possible new approaches to teaching people about science and technology. We are exploring the implications of this work for the design of intelligent learning environments. The domain of application is electrical circuits, but the approach can be generalized to other subjects. Our prototype instructional system is based upon a progression of qualitative models of electrical circuit behavior. These models enable the system to simulate circuit behavior and to generate causal explanations. They also serve as target mental models for the learner. The model progression is used to create problem sets that motivate successive refinements to the students' mental models. Acquisition of these models allows students, at all stages of learning, to solve interesting problems, such as circuit design and troubleshooting problems. The system enables students to employ different learning strategies and to manage their own learning. For instance, they can create and experiment with circuits, can attempt problems posed by the system, and can ask for feedback and coaching from the models. In pilot trials, the learning environment successfully taught novices to troubleshoot and to mentally simulate circuit behavior.

Fast heuristic algorithms for rectilinear steiner trees

A fundamental problem in circuit design is how to connectn points in the plane, to make them electrically common using the least amount of wire. The tree formed, a Steiner tree, is usually constructed with respect to the rectilinear metric. The problem is known to be NP-complete; an extensive review of proposed heuristics is given. An early algorithm by Hanan is shown to have anO(n logn) time implementation using computational geometry techniques. The algorithm can be modified to do sequential searching inO(n2) total time. However, it is shown that the latter approach runs inO(n3/2) expected time, forn points selected from anm×m grid. Empirical results are presented for problems up to 10,000 points.

Efficient Solution of Connectivity Problems on Hierarchically Defined Graphs

Using hierarchical definitions we can describe very large graphs in small spaces. In this paper we discuss how such succinct graph descriptions can be used to speed up the solution of graph problems. We present the bottom-up method that solves graph problems without expanding the hierarchical description. This allows solutions that are efficient in terms of the hierarchical graph description instead of the size of the expanded graph. We exemplify the method by giving efficient solutions to connectivity problems on hierarchical graphs. Our results have applications in computer-aided design for integrated circuit design and other engineering problems.

Logic circuit design with the aid of an automated reasoning program

As an example of a logic circuit design problem, we consider the two-inverter puzzle [1] which may be stated as follows:Using any number of AND, OR gates but no more than two NOT gates (inverters), design a logic circuit with three inputs i1, i2, i3 and three outputs o1, o2, 03 such that o1=NOT (il), o2=NOT (i2), o3=NOT (i3).

CMOS output buffers for megabit DRAMs

Output buffers for CMOS DRAMs are discussed and associated reliability risks and circuit design problems are shown. Concepts using true CMOS circuitry for output buffers are presented. Measurement results prove the feasibility of latch-up-free CMOS output structures, which have been implemented on a 4-Mb DRAM and use significantly less area than boosted NMOS concepts. >

An algorithm for calculating the values of the sensitivity of the secondary parameters of the time characteristics of electronic circuits

When solving many problems in circuit design, such as parametric optimization, the analysis and synthesis of tolerances, localization of faults, and the centering of the region of operation, it is necessary to determine the values of the sensitivities of the output characteristics to a change in the values of the parameters of the individual components of the electronic circuits. If we use as the output characteristics the currents in the components or the nodal potentials of the circuit, the required quantities can be found using well-known algorithms for modelling sensitivity [1, 2].

Device failure analysis in VLSI circuits due to missing flashes in mask fabrication process—A case study

Problems related to device failure in VLSI circuits have been studied from the design of an nMOS multi-circuit IC chip passing through the complete design-fabrication-evaluation sequence: computer aided design, PG tape generation, mask preparation, the fabrication process and evaluation. From critical analysis of the design-fabrication-evaluation sequence at every stage of the process, it has been noticed that there is another significant factor contributing to device failure, unusual missing exposures randomly distributed during the mask preparation which normally go unnoticed. This problem is apart from parametric processing problems, circuit design problems and random point defects associated with the normal causes of less than perfect yield.

An Integrated and Efficient Approach for MOS VLSI Statistical Circuit Design

An integrated and efficient approach is developed for automated statistical circuit design. One major problem in statistical circuit design for MOS VLSI is the prohibitively expensive computational requirements. The objective is to find realistic, accurate, and efficient solutions for use in the MOS VLSI design area. An automated statistical characterization system has been developed to characterize a large number of MOS devices to obtain statistical information on device parameters. A statistical model for MOS VLSI circuits has been developed in which only the interdie variations are considered, since they are much larger than the local intradie variations. Therefore, the set of statistical variables are different from the set of design parameters, and this leads to a resolution of the problem of dimensionality associated with statistical design. In this statistical model, variations in device length and width, oxide capacitance, and flat band voltage, have been shown to be the principal process factors responsible for the statistical variation of device characteristics. A scalable MOS model has been developed to represent changes in the device model parameters as functions of these principal factors. This accurate and simple statistical modeling approach uses only four statistical variables, and thus permits computationally efficient statistical parametric yield estimation (SPYE). The direct approach for transient sensitivity computation has been implemented in SPICE to allow very efficient computation of performance function sensitivities. An efficient technique for computing the yield gradient using the SPYE and transient sensitivity results is discussed and an example is presented to demonstrate its use in parametric yield optimization.

Broadbanding:Gain equalization directly from data

This paper begins by presenting a powerful method which is easy to apply to many broad-band circuit design problems. Anyone with a broad-band design problem, which in the narrow-band case amounts to finding a point inside of a certain circle (say on the Smith chart), might find the method here very useful (Section I). Gain equalization problems fall into this category and the main subject of this paper is a conceptually appealing, highly practical, and very flexible theory of gain equalization. The clever matching theory developed by Fano and Voula in principle handles passive one-ports well except for some difficulty in computing gain-bandwidth limitations. It converts the main problem into computing solutions to a system of nonlinear equations which are in practice so formidable that typical text book treatments [8], [9] never address the issue of solving them systematically. Also classical theory requires the load and gains to be specified as rational functions. Our theory does a good job on gain-bandwidth limitations, reduces all problems to ones of finding eigenvalues and eigenvectors of a given matrix, and only requires the load and gains be specified as data on a frequency band. Our theory is highly effective for multiports and so settles the old impedance matching problem for passive multiport circuits. The concrete results which we present here are: (1) Two numerically efficient ways to determine theoretical gain bandwidth limitations for one-ports and n-ports; (2) For one-ports a quick way to compute the frequency response function for the optimal coupling circuit directly from the answer obtained in (1). The recent advance of broad-band microwave technology has produced a need for more general and more flexible theories of gain equalization. The type of theory called for is based on measured data and avoids rational functions and spectral factorizations until late in the design process. One typically specifies a desired gain profile G(j\omega) and then wants to find the largest multiple \kappa G of it which is realizable. The procedure described herein is well suited to these needs since is requires only measured data and since determination of \kappa is automatic. A very different method for broadbanding which fills these needs was developed by Carlin [10]. It is a clever approach with quite a few compromises. One possible use of the lengthier rigorous procedure here would be to check the accuracy of Carlin's method. In addition to quantitative results we present some (much more easily learned) qualitative properties which every circuit (passive or active) designed to optimize gain possesses. They might be of considerable practical use in that any designer can learn them instantly and thereby obtain a certain (small) amount of general orientation very cheaply. The section on qualitative results, Section Ill, can be read independently of the rest of the paper (except for Fig. 1.1 and environs) and that might be best for some practical designers who have little taste for theory. Also in this paper we describe a certain viewpoint to the matching problem itself. From this perspective the matching problem is an elegant mathematical problem which fits solidly into a long line of classical mathematics. The classical mathematics underlies the computation of in Wiener's prediction theory. Our contention is that the matching problem is a very natural nonlinear analog of the classical prediction error problem. This formulation might broaden the appeal of impedance matching theory since it is easy to remember and is intriguing to the many systems theorists who are schooled in linear prediction theory (Section IV).

Algebraic formulation of circuit design problems

Algebraic formulation of circuit design problems

An interactive linear programming approach to model parameter fitting and worst case circuit design

An interactive linear programming-based method is proposed for optimization problems in worst case circuit design and device modeling. The method maximizes the impact of a single constrained Linear Programming (LP) step on a nonlinear design problem. The method thus becomes, for large problems, an economic first-order alternative to expensive completely convergent optimization algorithms. By fully exploiting the customary investment of IC designers in large change (and/or adjoint) sensitivity computation, the interactive (and inexpensive) LP design subproblem becomes a paradigm of the larger nonlinear design problem, in which critical tradeoffs and limitations become evident. In comparison with previously reported design methods, the key points of novelty are 1) the interactive role of the user in searching for a maximally effective LP step, 2) the combination of function minimization, step size minimization, and function inequality constraints in the LP step, and 3) linear prediction of all performance objective functions. Examples are given of the application of the method to the design and modeling of practical digital logic circuits.

A new algorithm for statistical circuit design based on quasi-Newton methods and function splitting

A new algorithm for the zero tolerance, fixed tolerance, and variable tolerance problems of optimal circuit design is presented. It is a minimax quasi-Newton method based on an algorithm of Powell for nonlinear constrained optimization. The new algorithm employs a new exact penalty function and a new efficient semidefinite quadratic program to determine the quasi-Newton step. In addition we use for the tolerance problems a method called function splitting to regularize the minimax problem. The algorithm is very efficient and examples are given which exhibit its super-linear convergence on regular and nonregular problems from the literature and on a practical worst-case circuit design problem.