Circuit Cover Research Articles

Circuit Covers of Signed Eulerian Graphs

A signed circuit cover of a signed graph is a natural analog of a circuit cover of a graph, and is equivalent to a covering of its corresponding signed-graphic matroid with circuits. It was conjectured that a signed graph whose signed-graphic matroid has no coloops has a 6-cover. In this paper, we prove that the conjecture holds for signed Eulerian graphs.

Signed Circuit Cover of Bridgeless Signed Graphs

Let $$(G, \sigma )$$ be a 2-edge-connected flow-admissible signed graph. In this paper, we prove that $$(G,\sigma )$$ has a signed circuit cover with length at most 3|E(G)|.

Shortest circuit covers of signed graphs

A shortest circuit cover F of a bridgeless graph G is a family of circuits that covers every edge of G and is of minimum total length. The total length of a shortest circuit cover F of G is denoted by SCC(G). For ordinary graphs (graphs without sign), the subject of shortest circuit cover is closely related to some mainstream areas, such as, Tutte's integer flow theory, circuit double cover conjecture, Fulkerson conjecture, and others. For signed graphs G, it is proved recently by Máčajová, Raspaud, Rollová and Škoviera that SCC(G)≤11|E| if G is s-bridgeless, and SCC(G)≤9|E| if G is 2-edge-connected. In this paper this result is improved as follows,SCC(G)≤|E|+3|V|+z where z=min⁡{23|E|+43ϵN−7,|V|+2ϵN−8} and ϵN is the negativeness of G. The above upper bound can be further reduced if G is 2-edge-connected with even negativeness.

Circuit Decompositions and Shortest Circuit Coverings of Hypergraphs

It is one of fundamental theorems in graph theory that every even graph has a circuit decomposition. This classical result for ordinary graphs is extended in this paper for uniform bridgeless hypergraphs if the degree of every vertex is even. One of major open problems for shortest circuit cover was a conjecture proposed by Itai and Rodeh (Automata, Languages and Programming, Lecture Notes in Computer Science, vol. 62, pp. 289–299. Springer, Berlin, 1978) that every bridgeless graph G has a circuit cover of total length at most $$|E|+|V|-1$$ . This conjecture was solved by Fan (J Combin Theory Ser B 74:353–367, 1998) for ordinary graphs, and is extended in this paper for bridgeless hypergraphs.

Short signed circuit covers of signed graphs

A signed graph G is a graph associated with a mapping σ: E(G)→{+1,−1}. An edge e∈E(G) is positive if σ(e)=1 and negative if σ(e)=−1. A circuit in G is balanced if it contains an even number of negative edges, and unbalanced otherwise. A barbell consists of two unbalanced circuits joined by a path. A signed circuit of G is either a balanced circuit or a barbell. A signed graph is coverable if each edge is contained in some signed circuit. An oriented signed graph (bidirected graph) has a nowhere-zero integer flow if and only if it is coverable. A signed circuit cover of G is a collection F of signed circuits in G such that each edge e∈E(G) is contained in at least one signed circuit of F; The length of F is the sum of the lengths of the signed circuits in it. The minimum length of a signed circuit cover of G is denoted by scc(G). The first nontrivial bound on scc(G) was established by Máčajová et al., who proved that scc(G)≤11|E(G)| for every coverable signed graph G, which was recently improved by Cheng et al. to scc(G)≤143|E(G)|. In this paper, we prove that scc(G)≤256|E(G)| for every coverable signed graph G.

Cycle covers (II) – Circuit chain, Petersen chain and Hamilton weights

The Circuit Double Cover Conjecture is one of the most challenging open problems in graph theory. The main result of the paper is related to the characterization of circuit chain structure, which has been one of the most popular approaches to the conjecture. Let G be a bridgeless cubic graph associated with an eulerian weight w:E(G)→{1,2} such that (G,w) does not have a faithful circuit cover. If, for every weight 2 edge e0 of (G,w), the eulerian weighted graph (G−e0,w) has a faithful circuit cover and (G,w) has no removable circuit avoiding e0, then it was proved (Alspach et al., 1993 [1] or 1994 [2]) that G contains a Petersen minor. It was further conjectured by Fleischner and Jackson (1988) that this graph G must be the Petersen graph. This conjecture was verified (JCTB 2010) recently under the assumption of the Hamilton weight conjecture. These two earlier results are further strengthened in this paper as follows. If, for a given weight 2 edge e0, the eulerian weighted graph (G−e0,w) has a faithful circuit cover and (G,w) has no removable circuit avoiding e0, then, under the assumption of the Hamilton weight conjecture, G must be a Petersen chain. With a much weaker requirement “for a givene0” instead of “for everye0”, this strengthened result (structure of circuit chain joining a missing edge) is expected to be much more useful in future studies about circuit covering problems.

Circuit Covers of Signed Graphs

We introduce the concept of a signed circuit cover of a signed graph. A signed circuit cover is a natural analog of a circuit cover of a graph and is equivalent to a covering of the corresponding signed graphic matroid with circuits. As in the case of graphs, a signed graph has a signed circuit cover only when it admits a nowhere-zero integer flow. In the present article, we establish the existence of a universal coefficient such that every signed graph G that admits a nowhere-zero integer flow has a signed circuit cover of total length at most . We show that if G is bridgeless, then , and in the general case .

Synthesis of Adaptable Hybrid Adders for Area Optimization under Timing Constraint

Satisfying the timing constraint is the utmost concern in the integrated circuit design and it is true that most critical timing paths in a circuit cover one or more arithmetic components such as adder, subtractor, and multiplier of which addition logic is commonly involved. This work addresses the problem of redesigning the addition logic (in a form of hybrid adder) on a critical timing path to meet the timing constraint while minimally allocating the required addition logic. Unlike the conventional hybrid adder design schemes in which they assume uniform or specific patterns of input signal arrival times and minimize the latest timing of the output signals, our work extracts the required timing of each output signal as well as the input arrival times directly from the circuit and resynthesizes the addition logic by creating a customized hybrid adder that is best suited, in terms of logic area, for meeting the timing constraint of the circuit. Specifically, we propose a systematic approach of hybrid adder design exploration, basically following the principle of dynamic programming with well-controlled pruning techniques. This work is realistic and practically very useful in that it can be used as a timing optimizer to the computation-intensive circuits with a tight timing budget. We provide a set of diverse experimental data to show how much the proposed hybrid adder scheme is effective in meeting or reducing timing while maintaining the circuit area as minimal as possible.

Cycle covers (I) – Minimal contra pairs and Hamilton weights

Let G be a bridgeless cubic graph associated with an eulerian weight w : E ( G ) ↦ { 1 , 2 } . A faithful circuit cover of the pair ( G , w ) is a family of circuits in G which covers each edge e of G precisely w ( e ) times. A circuit C of G is removable if the graph obtained from G by deleting all weight 1 edges contained in C remains bridgeless. A pair ( G , w ) is called a contra pair if it has no faithful circuit cover, and a contra pair ( G , w ) is minimal if it has no removable circuit, but for each weight 2 edge e, the graph G − e has a faithful circuit cover with respect to the weight w. It is proved by Alspach et al. (1994) [2] that if ( G , w ) is a minimal contra pair, then the graph G must contain a Petersen minor. It is further conjectured by Fleischner and Jackson (1988) [5] that this graph G must be the Petersen graph itself (not just as a minor). In this paper, we prove that this conjecture is true if every Hamilton weight graph is constructed from K 4 via a series of ( Y → △ ) -operations.

Paintshop, odd cycles and necklace splitting

The following problem has been presented in [T. Epping, W. Hochstättler, P. Oertel, Complexity results on a paint shop problem, Discrete Applied Mathematics 136 (2004) 217–226] by Epping, Hochstättler and Oertel: cars have to be painted in two colors in a sequence where each car occurs twice; assign the two colors to the two occurrences of each car so as to minimize the number of color changes. More generally, the “paint shop scheduling problem” is defined with an arbitrary multiset of colors given for each car, where this multiset has the same size as the number of occurrences of the car; the mentioned article states two conjectures about the general problem and proves its NP-hardness. In a subsequent paper in [P. Bonsma, Th. Epping, W. Hochstättler, Complexity results for restricted instances of a paint shop problem for words, Discrete Applied Mathematics 154 (2006) 1335–1343], Bonsma, Epping and Hochstättler proved its APX-hardness and noticed the applicability of some classical results in special cases. We first identify the problem concerning two colors as a minimum odd circuit cover problem in particular graphs, exactly situating the problem. A resulting two-way reduction to a special minimum uncut problem leads to polynomial algorithms for subproblems, to observing APX-hardness through MAX CUT in 3-regular graphs, and to a solution with at most 3/4th of all possible remaining color changes (when all obliged color changes have been made). For the general problem concerning an arbitrary number of colors, we realize that the two aforementioned conjectures are corollaries of the celebrated “necklace splitting” theorem of Alon, Goldberg and West.

Minmax relations for cyclically ordered digraphs

We prove a range of minmax theorems about cycle packing and covering in digraphs whose vertices are cyclically ordered, a notion promoted by Bessy and Thomassé in their beautiful proof of the following conjecture of Gallai: the vertices of a strongly connected digraph can be covered by at most as many cycles as the stability number. The results presented here provide relations between cycle packing and covering and various objects in graphs such as stable sets, their unions, or feedback vertex- and arc-sets. They contain the results of Bessy and Thomassé with simple algorithmic proofs, including polynomial algorithms for weighted variants, classical results on posets extending Greene and Kleitman's theorem (that in turn contains Dilworth's theorem), and a common generalization of these. The most general minmax results concern the maximum number of vertices of a k-chromatic subgraph ( k ∈ N ) —as a consequence, this number is greater than or equal to the minimum of | X | + k | C | , running on subsets of vertices X and families of cycles C covering all vertices not in X, in strongly connected digraphs. This is the “circuit cover” version of a conjecture of Linial (like Gallai's conjecture is the circuit cover version of the Gallai–Milgram theorem, meaning that path partitions are replaced by circuit covers under strong connectivity); we also deduce the circuit cover version of a conjecture of Berge on path partitions; these conjectures remain open, but the proven statements also bound the maximum size of a k-chromatic subgraph, contain Gallai's conjecture, and Bessy and Thomassé's theorems. All presented minmax relations are proved using cyclic orders and a unique elementary argument based on network flows—algorithmically only shortest paths and potentials in conservative digraphs—varying the parameters of the network flow model. In this way antiblocking and blocking relations can be established, leading to a general polyhedral phenomenon—a combination of “integer decomposition, integer rounding” and “dual integrality”—that also contains the matroid partition theorem and Dilworth's theorem. We provide a common reason for all these minmax equalities to hold and some possible other ones which satisfy the same abstract properties.

On the Circuit Cover Problem for Mixed Graphs

The circuit cover problem for mixed graphs (those containing edges and/or arcs) is defined as follows. Given a mixed graph M with a nonnegative integer weight function p on its edges and arcs, decide whether (M, p) has a circuit cover, that is, a list of circuits in M such that every edge (arc) e is contained in exactly p(e) circuits of the list. In the special case when M is a directed graph (contains only arcs), the problem is easy, but when M is an undirected graph not many results are known. For general mixed graphs this problem was shown to be NP-complete by Arkin and Papadimitriou in 1986. We prove that this problem remains NP-complete for planar mixed graphs. Furthermore, we present a good characterization for the existence of a circuit cover when M is series-parallel (a similar result holds for the fractional version). We also describe a polynomial algorithm to find such a circuit cover, when it exists. This is an ellipsoid-based algorithm whose separation problem is the minimum circuit problem on series-parallel mixed graphs, which we show to be polynomially solvable. Results on two well-known combinatorial problems, the problem of detecting negative circuits and the problem of finding shortest paths, are also presented. We prove that both problems are NP-hard for planar mixed graphs.

Circuit Decompositions of Eulerian Graphs

Let G be an eulerian graph. For each vertex v ∈ V ( G ), let P ( v ) be a partition of the edges incident with v and set P =∪ v ∈ V ( G ) P ( v ), called a forbidden system of G . We say that P is admissible if | P ∩ T |⩽ 1 2 | T | for every P ∈ P and every edge cut T of G . H. Fleischner and A. Frank (1990, J. Combin. Theory Ser. B 50 , 245–253) proved that if G is planar and P is any admissible forbidden system of G , then G has a circuit decomposition F such that | C ∩ P |⩽1 for every C ∈ F and every P ∈ P . We generalize this result to all eulerian graphs that do not contain K 5 as a minor. As a consequence, a conjecture of Sabidussi is settled for graphs that do not contain K 5 as a minor. Also, as a byproduct, our proof provides a different approach to the circuit cover theorem of B. Alspach, L. A. Goddyn, and C.-Q. Zhang (1994, Trans. Amer. Math. Soc. 344 , No. 1, 131–154).

Matroids with the Circuit Cover Property

We verify a conjecture regarding circuits of a binary matroid. Acircuit coverof a integer-weighted matroid (M,p) is a list of circuits ofMsuch that each elementeis in exactlyp(e) circuits from the list. We characterize those binary matroids for which two obvious necessary conditions for a weighting (M,p) to have a circuit cover are also sufficient.

Proofs of Two Minimum Circuit Cover Conjectures

LetGbe a 2-edge-connected graph withmedges andnvertices. The following two conjectures are proved in this paper. (i) The edges ofGcan be covered by circuits of total length at mostm+n−1. (ii) The vertices ofGcan be covered by circuits of total length at most 2(n−1), wheren⩾2.

The construction and reduction of strong snarks

Let G be a 3-regular graph and let w be a weight function, w : E( G) → {1, 2}, for which the edges of weight 2 form a 1-factor of G. If w can be choosen such that there does not exist a circuit cover C for ( G, w) in which each edge of G is contained in w( e) circuits of C then G is called a strong snark. Several methods are known for constructing snarks, and the reverse process has also been studied, see for example Cameron et al. (1987). We study the decomposition and construction of strong snarks.

A unified approach for fault simulation of linear mixed-signal circuits

The rapidly evolving role of analog signal processing has spawned off a variety of mixed-signal circuit applications. The integration of the analog and digital circuits has created a lot of concerns in testing these devices. This paper presents an efficient unified fault simulation platform for mixed-signal circuits while accounting for the imprecision in analog signals. While the classical stuck-at fault model is used for the digital part, faults in the analog circuit cover catastrophic as well as parametric defects in the passive and active components. A unified framework is achieved by combining a discretized representation of the analog circuit with the Z-domain representation of the digital part. Due to the imprecise nature of analog signals, an arithmetic distance based fault detection criterion and a statistical measure of digital fault coverage are proposed.

Circuit Coverings of Graphs and a Conjecture of Pyber

An equivalent statement of the circuit double cover conjecture is that every bridgeless graph G has a circuit cover such that each vertex v of G is contained in at most d ( v ) circuits of the cover, where d ( v ) is the degree of v . Pyber conjectured that every bridgeless graph G has a circuit cover such that every vertex of G is contained in at most Δ ( G ) circuits of the cover, where Δ ( G ) is the maximum degree of G . This paper affirms Pyber′s conjecture by establishing an intermediate result, namely that every bridgeless graph G has a circuit cover such that each vertex v of G is contained in at most d ( v ) circuits of the cover if d ( v ) ≥ 3 and in at most three circuits of the cover if d ( v ) = 2. Our proofs rely on results on integer flows.

Graphs with the Circuit Cover Property

Graphs with the Circuit Cover Property

Shortest Circuit Covers of Cubic Graphs

We show that the edge set of a bridgeless cubic graph G can be covered with circuits such that the sum of the lengths of the circuits is at most 6439|E(G)|. Stronger results are obtained for cubic graphs of large girth.