Circuit Applications Research Articles

Investigation of W/L ratio on the performance of ZnO transistors and inverters

Abstract Oxide transistors have attracted considerable attention in the field of integrated circuits. In this work, ZnO transistors were fabricated using atomic layer deposition process, with various width-to-length (W/L) ratios of 100/10 μm, 50/10 μm, 20/5 μm, 10/5 μm, and 10/10 μm. Among them, the ZnO transistor with a W/L ratio of 10/10 μm demonstrated superior electrical performance, including a field-effect mobility of 37.65 cm²V-1s-1, a subthreshold swing of 112.50 mV/decade, and a turn-on voltage of -0.50 V. Additionally, n-type ZnO transistors were used to design inverter circuits, where the voltage gain was found to be inversely correlated with the W/L ratio of the load transistor. A maximum voltage gain of 59.33 V/V was achieved at a supply voltage of 5 V using a load transistor with a W/L ratio of 10/5 μm. These results indicate that ZnO transistors, with optimized design, offer promising performance for future integrated circuit applications.

The camera and readout for the Trinity Demonstrator and the EUSO-SPB2 Cherenkov telescope

We developed a modular silicon photomultiplier camera to detect Earth-skimming PeV to EeV tau neutrinos with the imaging atmospheric Cherenkov technique. We built two cameras, a 256-pixel camera for the Trinity Demonstrator located on Frisco Peak, Utah, and a 512-pixel camera for the Extreme Universe Observatory on a Super-Pressure Balloon II (EUSO-SPB2) Cherenkov Telescope. The front-end electronics are based on the Multipurpose Integrated Circuit (eMUSIC) Application Specific Integrated Circuits (ASICs), and the camera signals are sampled and digitized with the 100MS/s and 12-bit ASIC for General Electronics for TPC (AGET) system. Both cameras are liquid-cooled. We detail the camera concept and the results from characterizing the SiPMs, bench testing, and calibrating the two cameras.

Efficient design of a reversible 2-to-4 decoder in quantum-dot cellular automata using Toffoli gates

This research presents an optimized design of a 2-to-4 decoder in Quantum-dot Cellular Automata (QCA) using a new formula developed from the Reversible. The proposed QCA decoder architecture employs 112 cells and occupies an area of 0.13μm², achieving a significant reduction in size compared to previous designs. The circuit is designed using a single-layer approach, enhancing its efficiency and minimizing power dissipation. Simulation results using the QCA Designer simulator version 2.0.3 demonstrate the enhanced functionality of the suggested decoder in regard to functionality and also efficiency, making it a promising candidate for future nanoscale integrated circuit applications.

Investigation of Device- and Circuit-Level Reliability of Inverse-Mode Silicon-Germanium Heterojunction Bipolar Transistors

The reliability of inverse-mode silicon-germanium (SiGe) heterojunction bipolar transistors (HBTs) under dc stress and its potential impact on the performance of basic analog amplifiers are investigated. In order to properly reflect the stress effects in various circuit applications, the degradations under three different configurations (active bias, diode connection, and off state) were experimentally characterized with the stress voltages applied up to 3000 s for each case. Based on the changes in the Gummel response, the degradations in device parameters such as current gain (β), transconductance (gm), and base-to-emitter resistance (rπ) were extracted and compared with the forward-mode counterpart. In addition, with the use of a small-signal equivalent model of a SiGe HBT, simple single-stage analog amplifiers were simulated as representative examples and their circuit-level performance metrics including gain and bandwidth were studied to estimate degradation characteristics with accumulated stress. It was found that transimpedance gain decreases and operation bandwidth increases to different levels due to device degradation, whereas a voltage amplifier exhibited much less changes.

Linearity analysis of FE-based graded channel junctionless FET obtaining negative capacitance for low power applications

This paper reports ferroelectric (FE) oxide based graded-channel junctionless FET featuring the negative capacitance effects in nano-scale regime. The linearity nature of its response is analysed on the basis of third order interception point (PIP3), harmonic interception voltages of 2nd and 3rd orders (VIP2, VIP3) and intermodulation distortion (IMD3). Influence of fundamental device’s parameters such as, gate and underlap length, ferroelectric oxide thickness, graded channel doping and operating temperature on its linear behavior is observed and analysed in detail. The subthreshold slope is also found to go below 60mV/dec for optimum features, obtaining the NC characteristics. In its circuit application part, a cascode amplifier is designed using the proposed device showing variations due to the change in the proposed device dimensions. The proposed device is designed and simulated using Silvaco ATLAS device simulator, which is calibrated with the available experimental results. Therefore, the present study is quite relevant in recent days for low power analog applications.

Analytical modeling of III-V heterojunction source-all-around vertical tunnel FET and its inverter circuit application

Abstract This paper presents a comprehensive analytical modeling framework for the III-V heterojunction source-all-around vertical tunnel field-effect transistor (SAA V-TFET). Using Kane's model, our approach involves solving Poisson's equations to obtain a continuous surface potential profile, followed by the derivation of drain current. These models demonstrate excellent accuracy across all operating regions, precisely predicting the potential profile, output, and transfer characteristics of SAA V-TFETs. We implemented the models in MATLAB and validated them against Sentaurus TCAD simulations. Furthermore, we present a comprehensive performance analysis of SAA V-TFET-based digital inverters.

Three-Phase Bridge Fully-Controlled Rectifier Circuit Design Based On Digital Integrated Circuits

This paper aims to design and analyze a three-phase fully controlled bridge rectifier circuit. The paper first introduces the basic principles and advantages of the three-phase fully controlled bridge rectifier circuit and then elaborates on five key aspects of the design: transformer design, thyristor selection, thyristor protection design, trigger circuit design, and trigger circuit power supply design. During the design process, parameters such as the motor’s rated power, voltage, current, and resistance were considered to ensure that the selection of thyristor parameters and protective measures meet the needs of practical applications. In addition, the paper discusses the design of synchronous transformers, phase selection, the application of the KJ004 trigger circuit, and the design of the trigger circuit power supply. Finally, the circuit was simulated using Matlab simulation tools, the circuit design was optimized, and satisfactory pulse waveforms and output waveforms were obtained by adjusting the experimental time. The research in this paper provides theoretical basis and practical guidance for the optimized design of three-phase fully controlled bridge rectifier circuits.

Performance enhancement of solution-processed organic thin-film transistors incorporating an improved Corbino structure

The solution-processed organic thin-film transistors (OTFTs) with a minimal device footprint and improved performance are desirable for flexible electronics and other circuit applications. It is demonstrated that the enhanced performance can be achieved for solution-processed OTFTs by adopting an improved Corbino structure. The bottom-gate bottom-contact OTFTs of W/L ratio of 500 are fabricated using the standard poly-3-hexylthiophene (P3HT) as a semiconductor with an improved interdigitated pseudo-Corbino (IPC) structure. The exhibited IPC structure is a combination of interdigitated structure in the enclosed-Corbino design to achieve infinite output resistance, suppressed parasitic leakage current, and high ON current by accommodating a high W/L ratio in a minimal device footprint. For the fabricated solution-processed OTFTs, infinite output resistance with an OFF-current of the order of 10−12 A and an ON/OFF ratio of drain current of the order of 107 is achieved. Incorporating an enhanced hexamethyldisilazane treatment of the SiO2 gate dielectric improves the ON/OFF ratio to a record value of 108 and the mobility of the order of 10−2 cm2/Vs for P3HT. Implementation of IPC-TFT structure for intentionally chosen moderate-mobility, solution-processed P3HT semiconductor results in a consistent low OFF-current, high ON/OFF ratio, and infinite output resistance with excellent device-to-device uniformity.

Drain self-blocking ambipolar transistors for complementary circuit applications

The development of complementary metal-oxide-semiconductor field-effect transistor (CMOSFET) based on two-dimensional (2D) materials offers an important opportunity to reduce static power and increase the integration density of integrated circuits. One promising approach to realize these CMOSFETs is to employ ambipolar 2D materials as channel materials with designed device structure to control the carrier transport properties for CMOSFET characteristics. However, these devices always suffer from complex multi-gate electrode structure, and hence face challenges in complicated inter-connection design and excessive voltage source requirement for circuit implementation. Here, we develop a three-terminal CMOSFET using ambipolar 2D material based on the drain electric field-induced carrier injection self-blocking mechanism. The designed drain electrode can effectively suppress carrier injection from the drain to the channel material, while the gate voltage can only regulate carrier injection in the source region. As a result, we can configure the device as either N-field-effect transistors (FET) or P-FET with a high current on/off ratio of over 105 by adjusting the three voltages (gate, source, and drain). Furthermore, we utilize these devices to demonstrate multifunctional wave modulator, low-static-power logic inverter (<5 pW), and combinational logic computing in the form of a compact complementary circuit. Our work would explore an efficient approach for implementing complementary circuits using 2D materials.

Ultralow-Power Circuit and Sensing Applications Based on Subthermionic Threshold Switching Transistors.

The most recent breakthrough in state-of-the-art electronics and optoelectronics involves the adoption of steep-slope field-effect transistors (FETs), promoting sub-60 mV/dec subthreshold swing (SS) at ambient temperature, effectively overcoming "Boltzmann limit" to minimize power consumption. Here, a series integration of nanoscale copper-based resistive-filamentary threshold switch (TS) with the IGZO channel-based FET is used to develop a TS-FET, in which the turn-on characteristics exhibit an abrupt transition over five decades, with an extremely low SS of 7 mV/dec, a high on/off ratio (>109), and ultralow leakage current (40-fold decrease), ensuring excellent repeatability and device yield. Unlike previous device-centric studies, this work highlights potential circuit applications (logic-inverter, pulse-sensor amplification, and photodetector) based on TS-FET. The sharp transition behavior of TS-FET enables the establishment of logic inverters with a high voltage gain of ≈800, with a circuit-level demonstration achieving a bias-independent record-high intrinsic gain (>1000). A wearable pulse sensor integrated with an amplifier circuit ensured the precise amplification of electrophysical signals by 450 times. In addition, the application of a TS-FET-based photodetector features high responsivity (1.08 × 104 mA/W) and detectivity (1.03 × 1020 Jones). The low-power strategy of TS-FETs is promising for the development of energy-efficient integrated circuits alongside sensor-interconnected biomedical applications in wearable technology.

Analysis of etched drain based Cylindrical agate‐all‐around tunnel field effect transistor based static random access memory cell design

AbstractThis paper aims to propose a novel method for designing an static random access memory (SRAM) cell using an etched drain based Cyl GAA TFET with a hetero‐substrate material and an elevated density strip. The aim is to reduce power dissipation and improve stability, as demonstrated through analysis utilizing static noise margin (SNM) as well as N‐curve methods. With respect to the 16 nm MOSFET based SRAM cell, the proposed device‐based SRAM cell shows significant improvements with a 68.305% reduction in leakage power, a 15.58% increase in static voltage noise margin (SVNM), an 8.623% increase in static current noise margin (SINM), an 8.152% increase in write trip voltage (WTV), a 12.86% increase in write trip current (WTI), a 27.62% increase in static power noise margin (SPNM), and a 19.95% increase in write trip power (WTP). The design is implemented and analyzed using Cadence Virtuoso software, and a novel approach of look up tables and Verilog A is utilized for the device to circuit application. These results indicate promising advancements in the design of SRAM cells, which could have significant implications for the development of advanced computer systems.

Optimization of Impact Ionization in Metal–Oxide–Semiconductor Field-Effect Transistors for Improvement of Breakdown Voltage and Specific On-Resistance

For the past few decades, metal–oxide–semiconductor field-effect transistors (MOSFETs) have been the most important application in IC circuits. In certain circuit applications, the breakdown voltage and specific on-resistance serve as key electrical parameters. This article introduces a readily accessible approach to enhance the source–drain breakdown voltage (BVDS) of MOSFETs based on the Bipolar-CMOS-DMOS (BCD) platform without extra costs. By attentively refining the process steps and intricacies of the doping procedures, the breakdown voltages of NMOS and PMOS experienced increments of 3.4 V and 4.6 V, translating to enhancements of 31.5% and 50.3%. Parallel simulations offer insightful mechanistic explanations through simulation tools, facilitating superior outcomes. This initiative lays significant groundwork for the advancement of a comprehensive BCD process development framework.

Multi-wing chaotic system based on meminductor and its application in image encryption

Meminductor is a novel type of nonlinear device following the memristor, characterized by its memory properties. Currently, research on meminductors is still in its infancy, with their physical devices yet to be formally realized. Therefore, conducting fundamental research on their nonlinear circuit properties and applications is of great significance. In this paper, a new multi-wing chaotic system is proposed based on the mathematical model of a magnetically controlled meminductor. By varying the values of its parameters, the system can generate two-wing, three-wing, and four-wing chaotic attractors. Various analytical methods are employed to study the dynamical behaviours of the proposed chaotic system. The results demonstrate that the system is highly sensitive to its initial conditions and control parameters, which makes it suitable for image encryption. Based on the new system, we propose a new algorithm for image encryption that combines the newly established four-dimensional multi-wing chaotic system with bit plane decomposition technique, firstly, the high four-bit planes containing 94% image information are disordered by S-type permutation, then the disordered bit planes perform operation of XOR with the random matrix generated by chaotic sequences, and finally, the encrypted image is obtained by merging the bit planes.

Single ambipolar OECT-based inverter with volatility and nonvolatility on demand.

Organic electrochemical transistor (OECT)-based inverter introduces new prospects for energy-efficient brain-inspired artificial intelligence devices. Here, we report single-component OECT-based inverters by incorporating ambipolar p(gDPP-V). Notably, p(gDPP-V) shows state-of-the-art ambipolar OECT performances in both conventional (p/n-type mode transconductance of 29/25 S cm-1) and vertical (transconductance of 297.2/292.4 μS μm-2 under p/n operation) device architectures. Especially, the resulting highly stable vertical OECT-based inverter shows a high voltage gain of 105 V V-1 under a low driving voltage of 0.8 V. The inverter exhibits undiscovered voltage-regulated dual mode: volatile receptor and nonvolatile synapse. Moreover, applications of physiology signal recording and demonstrations of NAND/NOR logic circuits are investigated within the volatile feature, while neuromorphic simulations with a convolutional neural network and image memorizing capabilities are explored under the nonvolatile behavior. The ambipolar OECT-based inverter, capable of both volatile and nonvolatile operations, provides possibilities for the applications of reconfigurable complementary logic circuits in novel neuromorphic computing paradigms.

Compact design of universal gates with non-aligned gate technology and assessment of its performance in a TCAD Environment

ABSTRACT This paper proposes a technology computer-aided design (TCAD) of a compact single-device NAND and NOR logic gates in 215 nm device length along with speed and power performance results. The universal gates are designed with non-aligned double gate technology, and this helps to reduce the transistor count, giving a compact design structure. The static characteristics and input pattern sensitivity of the NAND and NOR structures are investigated in this work. By using graphical method, the optimal supply voltage of the universal gates was determined. The optimal supply voltage of the NAND gate and NOR gate was 0.9 V and 0.84 V, respectively, at an input frequency of 1 GHz. Further, the device scalability of the proposed structures was analysed. When compared to the past work, the proposed NAND gate and NOR gate improves delay performance by 25.02% and 35.63%, respectively. Additionally, a reduction of 10% and 16% in its supply voltage is achieved. Therefore, the proposed gate has potential to operate at higher frequency with reduced supply voltage, making them suitable in circuit applications.

Exploring DNA Computers: Advances in Storage, Cryptography and Logic Circuits.

Over the last four decades, research on DNA as a functional material has primarily focused on its predictable conformation and programmable interaction. However, its low energy consumption, high responsiveness and sensitivity also make it ideal for designing specific signaling pathways, and enabling the development of molecular computers. This review mainly discusses recent advancements in the utilization of DNA nanotechnology for molecular computer, encompassing applications in storage, cryptography and logic circuits. It elucidates the challenges encountered in the application process and presents solutions exemplified by representative works. Lastly, it delineates the challenges and opportunities within this filed.

Event-triggered sliding mode control for networked T–S fuzzy delayed systems against random injection attacks

This paper investigates the event-triggered sliding mode control (SMC) problem for networked T–S fuzzy delayed systems subject to random injection attacks, where the event-triggered mechanism (ETM) is introduced to alleviate data congestion and improve network efficiency. Under an open network environment, malicious attackers may randomly inject false information into the controller–actuator channel to compromise the integrity of the data. A new fuzzy sliding mode controller is constructed based on a non-parallel distributed compensation strategy, which introduces the distribution information of the attack probability. Then, the membership function dependent (MFD) analysis technique is adopted to reconstruct the membership functions in order to reduce the conservatism caused by the mismatch between the membership functions of fuzzy model and controller. Furthermore, the co-design conditions for the ETM and the fuzzy sliding mode controller are provided, which can ensure that the resulting closed-loop fuzzy system is mean-square exponentially ultimately bounded (EUB) and the sliding surface is reachable. Finally, a simulation experiment with tunnel diode circuit application is utilized to demonstrate the validity of the proposed SMC scheme.

An analytical I-V model of SiC double-gate junctionless MOSFETs

Silicon carbide(SiC) double gate junctionless metal oxide semiconductor field-effect transistors(DG JL MOSFETs) have attracted significant attention due to their ideal high temperature characteristics and radiation resistance. Therefore, it is meaningful to exploit an I-V model for SiC DG JL MOSFETs. In this article, we make a linear approximation to describe the relationship between the surface mobile charge density and the surface electron concentration of the device. Based on this approximation and using the one-dimensional Poisson’s equation, we solve for the potential distribution of a SiC DG JL MOSFET in the subthreshold region. From this solution, we derived a functional relationship between the surface mobile charge density in the channel and the channel quasi-Fermi potential. Then we successfully developed a unified I-V model for the SiC DG JL MOSFETs. Based on the drain to source current calculation formula, the calculation expressions for the device’s transconductance and output conductance are derived. By comparing our model with the results from the two-dimensional numerical simulation software Silvaco Atlas, our model’s calculations closely match the two-dimensional numerical simulation results from the subthreshold region to the accumulation region. This model has reference significance for SiC DG JL MOSFETs in the high temperature electronic circuit application field.

Broadband nonlinear refraction transients in C-doped GaN based on absorption spectroscopy

Optical nonlinear response and its dynamics of wide-bandgap materials are key to realizing integrated nonlinear photonics and photonic circuit applications. However, those applications are severely limited by the unavailability of both dispersion and dynamics of nonlinear refraction (NLR) via conventional measurements. In this work, the broadband NLR dynamics with extremely high sensitivity (λ/1000) can be obtained from absorption spectroscopy in GaN:C using the refraction-related interference model. Both the absorption and refraction kinetics are found to be significantly modulated by the C-related defects. Especially, we demonstrate that the refractive index change Δn of GaN:C is negative and can be used to realize all-optical switching applications owing to the large NLR and ultrafast switching time. The NLR under different non-equilibrium carrier distributions originates from the capture of electrons by CN+ defect state, while the absorption modulation originates from the excitation of tri-carbon defects. We believe that this work provides a better understanding of the GaN:C nonlinear properties and an effective solution to broadband NLR dynamics of transparent thin films or heterostructure materials.

Current Feedback Operation Amplifier Based on Floating Passive and Active Inductors in Filter Applications

This paper proposes using current feedback operation amplifiers (CFOAs) as an active filter in creating floating passive and active inductance simulators is a versatile and efficient solution for circuit design. CFOAs are popular for their high slew rate and wide bandwidth which makes them ideal candidates for applications demanding rapid response time alongside high frequencies. It is possible to customize these simulated inductances for different design specifics by changing certain external resistor values. The circuit comprises a trio of CFOAs, an earthed capacitor and three resistors, thus making it quite simple to put into practice at a cheap price. Experiments and LTSPICE simulations have been conducted to examine the performance of the circuit, and closely confirmed theoretical expectations. In other words, this confirms the trustworthiness and preciseness of the introduced floating active inductance simulator. Voltage-mode band-stop filtering is one real-world scenario where this circuit is used. This indicates that our proposed technique can have more applications than one in circuit design. This is further proof that our idea can be used in other circuits as well. In conclusion, using CFOAs in active filters for building a grounded passive active inductance simulator is a solid and effective answer to circuit designers. This makes it an appealing choice for numerous applications because of its simplicity in designing the network as well as its high performance and customizability. Circuit design and application can be greatly improved if more study is done in this field.