Parallel Chip Research Articles

Characteristics of the planar second-order high-Tc SQUID gradiometer

We have studied the planar-type single-layer second-order high-Tc SQUID gradiometer that detects the transverse field gradient, d2Bz/dx2. The gradiometer consists of three parallel-connected rectangular pickup loops that are directly coupled to a SQUID. The pickup loops are designed in such a way that the SQUID measures the difference in the differential screening currents of neighbouring pickup loops. The SQUID has either step-edge or bicrystal Josephson junctions. The gradiometer was made from a single layer of YBa2Cu3O7 film on a 1 cm × 1 cm chip. The response of the gradiometer was tested in various flux distributions generated by three identical multiturn film coils patterned on the same chip in parallel with each pickup loop. The balanced gradiometer responded sensitively only to the second-order field gradient. Reduction of the inductive coupling between loops improved the intrinsic balance.

Hyperspeed data acquisition for 3D computer vision metrology as applied to law enforcement

The use of conventional video cameras at standard broadcast rates permits 30 frame per second videocapture and recording. Even when moving events are recorded with fast shuttering to preclude blurring (e.g. 1000th second) each recorded consecutive stopped action still has a 33 millisecond interval between them. The reason for this is the finite time necessary to serially dump recorded information from the microchip sensor, and reinitialize the sensor for the next capture event. By designing a parallel video chip with multiple, independently capable segments for sensor input/output/re-initialization, the duration of the interval required for unloading and resetting the entire sensor is decreased by the number of discrete segments in the chip, and the number of unloading ports to transfer data. Silicon Mountain Design, Inc. (SMD) developed a 16 parallel channel output 512 by 512 by 8 bit digital video camera, and a suitable memory buffer to absorb 256 full images. This camera has the uniquely advantageous feature that no image data is absorbed while the camera discharges its image to the parallel output ports. With this parallel video camera it is possible to record events at 1000th second (or faster) continuously, or at least until the memory buffer fills. The use of structured light stereo numerical camera technology requires the collection of a series of video images, each video-image containing a different 'exposure' of an object with a different pattern of structured laser beams projected onto it. The complete series of images creates a temporal-spatial encoding of the laser beams necessary to calculate a 3-D numerical recreation of the object. By using a parallel video camera, the collection of a complete series is limited by the time it takes to expose each video-image, plus the time it takes to change the light pattern being projected. Using a rapid ferric liquid crystal electro-optic modulator with a 1 millisecond cycle time, and an SMD parallel video camera cycling at 1 millisecond, each pattern is projected and recorded in a cycle time of 1/500th second. An entire set of patterns can then be recorded within 1/60th second. This pattern set contains all the information necessary to calculate a 3-D map. The use of hyper-speed parallel video cameras in conjunction with high speed modulators enables video data rate acquisition of all data necessary to calculate numerical digital 3-D metrological surface data. Thus a 3-D video camera can operate at the rate of a conventional 2-D video camera. The speed of actual 3-D output information is a function of the speed of the computer, a parallel processor being preferred for the task. With video rate 3-D data acquisition law enforcement could survey crime scenes, obtain evidence, watch and record people, packages, suitcases, and record disaster scenes very rapidly.

Progress in CMOS integrated measurement systems

Selected micro- and nano-systems developed recently at the Physical Electronics Laboratory of ETH Zurich are reviewed: (i) a fluxgate microsystem for detection of the Earth's magnetic field; (ii) a capacitive chemical sensor microsystem for detection of volatile organic compounds in air; and (iii) a parallel scanning AFM chip. The micro- and nano-systems combine sensor structures and readout circuitry on a single chip and are fabricated using industrial CMOS technology in combination with post-processing micromachining and film deposition.

SPHERICAL SUBSPACE TRACKING ON SYSTOLIC ARRAYS

The spherical subspace tracker is a low complexity adaptive algorithm that converges to the dominant (or subdominant) subspace. Spherical subspace updating is a fast way to monitor slowly time-varying subspaces, which arise in high resolution direction of arrival tracking algorithms. In real time sonar and radar array processing applications, it becomes necessary to find parallel algorithms and pipelined architectures that provide high speed solutions to these tracking problems. In this paper the spherical subspace tracker is parallelized and mapped onto systolic array architectures. The arrays are ideally suited for implementation with custom VLSI or networks of available parallel numeric processing chips such as iWarps and TMS320C40s. C-language like cell programs specify the functionality and timing of the systolic array in concrete terms.

リアルタイムビジョン 超並列・超高速ワンチップビジョンとその応用

リアルタイムビジョン 超並列・超高速ワンチップビジョンとその応用

No polynomial bound for the period of the parallel chip firing game on graphs

The following (solitaire) game is considered: Initially each node of a simple, connected, finite graph contains a finite number of chips. A move consists in firing all nodes with at least as many chips as their degree, where firing a node corresponds to sending one of the node's chips to each one of the node's neighbors.

Multiplexed optical access to a VLSI circuit through a holographic microlens array

We describe the use of a holographic microlens array for broadcasting instructions optically to a massively parallel VLSI silicon chip. Thanks to Bragg selectivity, it is possible to distribute other optical signals besides instruction broadcasting, such as for example input data, by adjusting the directions and wavelengths of the various beams in such a way that some go through the holographic array undisturbed.

A 60 MBd, 480 Mb/s, 256 QAM decision-feedback equalizer in 1.2 mu m CMOS

Using a combination of architecture optimization techniques and unconventional circuit designs, a 60 MHz decision-feedback equalizer (DFE) chip is presented for high-bit-rate digital modem applications. The equalizer can accommodate quaternary phase-shift keying (QPSK), and 16, 64, and 256 quadrature amplitude modulation (QAM) and achieves a peak throughput rate of 480 MB/s. The chip contains four complex-valued programmable filter taps and incorporates coefficient updating circuitry for implementing the LMS adaptive algorithm with user-selectable adaptation step sizes. Cut-set retiming architecture techniques were used so that the chips could be cascaded to implement longer equalizer lengths without any speed degradation, and a circuit design technique called adaptively biased pseudo-NMOS logic (APNL) was adopted to reduce on-chip critical-path delays. The fully parallel chip architecture achieves a computational throughput of 1.44 billion operations per second (GOPS).< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Level-2 cache for high performance /390 μ-processors

A L2 cache chip design for high performance /390 μ-processors in a multiprocessor environment is presented. Design objectives, logic and technological implementation as well as measured results are discussed. The design features a 96 k Bytes L2 cache-, its associated directory- and LRU arrays, dataflow and control logic integrated on one CMOS standard cell chip with more than 6 million transistors. Its nominal operating frequency is 75 Mhz. 16 bytes wide memory and PU busses are serviced by operating two L2-cache chips in parallel.

Parallel chip firing games on graphs

We study the periodic behaviour of parallel dynamics associated with the chip firing game introduced by Spencer (1986). We prove that on trees the periods are of length one (fixed points) or two. For general graphs we give counter-examples where periods depend on the graph size. We also prove that the chip firing game may be used as an algorithm to evaluate logical functions, which shows that the dynamics have nontrivial computing capabilities. Finally, we study a related game on graphs.

Highly parallel residue arithmetic chip based on multiple-valued bidirectional current-mode logic

Discusses the implementation of a residue arithmetic circuit using multiple-valued bidirectional current-mode MOS technology. Each residue digit is represented by new multiple-valued coding suitable for highly parallel computation. By the coding, mod m/sub i/ multiplication can be simply performed by a shift operation. In mod m/sub i/ addition, radix-5 signed-digit (SD) arithmetic is employed for a high degree of parallelism and multiple-operand addition, so that high-speed arithmetic operations can be achieved. Finally, the mod7 three-operand multiply adder is designed and fabricated as an integrated circuit based on 10- mu m CMOS technology. >