Chip Scale Research Articles

An on-chip instrument for white blood cells classification based on a lens-less shadow imaging technique

Routine blood tests provide important basic information for disease diagnoses. The proportions of three subtypes of white blood cells (WBCs), which are neutrophils, monocytes, lymphocytes, is key information for disease diagnosis. However, current instruments for routine blood tests, such as blood cell analyzers, flow cytometers, and optical microscopes, are cumbersome, time consuming and expensive. To make a smaller, automatic low-cost blood cell analyzer, much research has focused on a technique called lens-less shadow imaging, which can obtain microscopic images of cells in a lens-less system. Nevertheless, the efficiency of this imaging system is not satisfactory because of two problems: low resolution and imaging diffraction phenomena. In this paper, a novel method of classifying cells with the shadow imaging technique was proposed. It could be used for the classification of the three subtypes of WBCs, and the correlation of the results of classification between the proposed system and the reference system (BC-5180, Mindray) was 0.93. However, the instrument was only 10 × 10 × 10 cm, and the cost was less than $100. Depending on the lens-free shadow imaging technology, the main hardware could be integrated on a chip scale and could be called an on-chip instrument.

Research for light source module of curved shape by Chip Scale Package technology

Research for light source module of curved shape by Chip Scale Package technology

Laser cutting sandwich structure glass–silicon–glass wafer with laser induced thermal–crack propagation

Silicon-glass devices are widely used in IC industry, MEMS and solar energy system because of their reliability and simplicity of the manufacturing process. With the trend toward the wafer level chip scale package (WLCSP) technology, the suitable dicing method of silicon-glass bonded structure wafer has become necessary. In this paper, a combined experimental and computational approach is undertaken to investigate the feasibility of cutting the sandwich structure glass-silicon-glass (SGS) wafer with laser induced thermal-crack propagation (LITP) method. A 1064nm semiconductor laser cutting system with double laser beams which could simultaneously irradiate on the top and bottom of the sandwich structure wafer has been designed. A mathematical model for describing the physical process of the interaction between laser and SGS wafer, which consists of two surface heating sources and two volumetric heating sources, has been established. The temperature stress distribution are simulated by using finite element method (FEM) analysis software ABAQUS. The crack propagation process is analyzed by using the J-integral method. In the FEM model, a stationary planar crack is embedded in the wafer and the J-integral values around the crack front edge are determined using the FEM. A verification experiment under typical parameters is conducted and the crack propagation profile on the fracture surface is examined by the optical microscope and explained from the stress distribution and J-integral value.

CSAC Characterization and Its Impact on GNSS Clock Augmentation Performance

Chip Scale Atomic Clocks (CSAC) are recently-developed electronic instruments that, when used together with a Global Navigation Satellite Systems (GNSS) receiver, help improve the performance of GNSS navigation solutions in certain conditions (i.e., low satellite visibility). Current GNSS receivers include a Temperature Compensated Cristal Oscillator (TCXO) clock characterized by a short-term stability (τ = 1 s) of 10−9 s that leads to an error of 0.3 m in pseudorange measurements. The CSAC can achieve a short-term stability of 2.5 × 10−12 s, which implies a range error of 0.075 m, making for an 87.5% improvement over TCXO. Replacing the internal TCXO clock of GNSS receivers with a higher frequency stability clock such as a CSAC oscillator improves the navigation solution in terms of low satellite visibility positioning accuracy, solution availability, signal recovery (holdover), multipath and jamming mitigation and spoofing attack detection. However, CSAC suffers from internal systematic instabilities and errors that should be minimized if optimal performance is desired. Hence, for operating CSAC at its best, the deterministic errors from the CSAC need to be properly modelled. Currently, this modelling is done by determining and predicting the clock frequency stability (i.e., clock bias and bias rate) within the positioning estimation process. The research presented in this paper aims to go a step further, analysing the correlation between temperature and clock stability noise and the impact of its proper modelling in the holdover recovery time and in the positioning performance. Moreover, it shows the potential of fine clock coasting modelling. With the proposed model, an improvement in vertical positioning precision of around 50% with only three satellites can be achieved. Moreover, an increase in the navigation solution availability is also observed, a reduction of holdover recovery time from dozens of seconds to only a few can be achieved.

Development and reliability study of 3D WLCSP for CMOS image sensor using vertical TSVs with 3:1 aspect ratio

3D wafer-level chip scale packaging (3D WLCSP) using via last through silicon via (TSV) technology is an ideal technology to meet small-form-factor, high I/O density, high-speed, short time to market and lower cost product requirements. In this study, process development and reliability evaluation of 3D WLCSP for CMOS Image Sensor (CIS) using vertical TSVs with 3:1 aspect ratio were presented. Key processes including wafer bonding, wafer backside grinding, silicon etch, bottom oxide etch, via cleaning, barrier/seed layer deposition, electroplating, redistribution layer (RDL) and ball grid array (BGA) formation were developed. Reliability of the developed WLCSP was characterized by various tests. The failed devices after reliability tests were analyzed using microstructure observation and finite element simulation for stress distribution of TSV structure. The results indicate that WLCSP with vertical via last scheme can provide a reliable, low-cost solution for the next-generation CIS requiring high density routing.

ACO-Based Thermal-Aware Thread-to-Core Mapping for Dark-Silicon-Constrained CMPs

The limitation on thermal budget in chip multiprocessor (CMP) results in a fraction of inactive silicon regions called dark silicon, which significantly impacts the system performance. In this paper, we propose a thread-to-core mapping method for dark-silicon-constrained CMPs to address their thermal issue. We first propose a thermal prediction model to forecast CMP temperature after the CMP executes a forthcoming application. Then, we develop an ant colony optimization-based algorithm to conduct the thread-to-core mapping process, such that the CMP peak temperature is minimized and, consequently, the probability of triggering CMP dynamic thermal management is decreased. Finally, we evaluate our method and compare it with the baseline (a standard Linux scheduler) and other existing methods (NoC-Sprinting, DaSiM mapping, and TP mapping). The simulation results show that our method gains good thermal profile and computational performance, and performs well with chip scaling. Specifically, it eliminates all thermal emergency time, outperforming all other methods, and gains million instructions per second improvement up to 12.9% against the baseline.

The Increasing Role of Polymers in Advanced Packaging - From Stress Buffer Layers to Wafer Level Underfills and Beyond

With the continued expansion of computing capability and reduction in technology node for advanced logic or memory devices the challenges encountered due to packaging also increase. Driven by Power, Performance and Area requirements of sub 14nm node devices and their associated system architectures, packaging solutions must also enable optimum performance whilst maintaining an affordable approach, especially within the mobile applications market. Due to this, the role of polymers within the integrated system of multi die packaging becomes ever more important. Polymers have become a vital enabler from both a technical and cost reduction viewpoint, where they have a role to play in various position within the integration scheme. Stress buffers layers are common, but we now move into the era of commercialized wafer level underfills, the use of silicone style materials for Chip Scale Packaging (CSP) to enable more flexible interconnects, Temporary Bonding Materials (TBM) compatible with alternative polymer materials, even pushing to the point of TBM compatibility with overmold materials. Even with all this research the thermal aspects of performance computing means we must also seek improved Thermal Interface Materials (TIMs) in addition to all of the afore mentioned materials.

基于回音壁腔光力系统的光学三极管

回音壁腔系统由于其高品质因子、小的模体积、以及简单的制造工艺而在光子器件方面有着潜在的应用。本文基于耦合的回音壁腔光力系统，通过光学泵浦-探测方案提出一种全光学三极管器件。该系统中透射信号由控制光场的功率所操控，而且信号场的放大和消逝可以通过控制栅极场的功率来实现，该器件表现出单光子光学三极管的行为。回音壁腔光力系统将在芯片尺度上的量子信息处理器件上有着潜在的应用。 Whispering gallery mode (WGM) cavities, due to their high-quality factors, small mode volumes, and simple fabrications, have potential applications in photonic devices. In this paper, we present an all-optical transistor based on a coupled realistic WGM cavity optomechanical system with an optical pump-probe scheme. In the system, the transmission of the signal field is manipulated by the optical control power, and the signal field can be efficiently attenuated or amplified depending on the power of a second gating (control) field, which indicates a promising candidate for single-photon transistors. This WGM cavity optomechanical system may have potential chip scale applications in on-chip quantum information processing devices.

Hybrid Airy plasmons with dynamically steerable trajectories.

With their intriguing diffraction-free, self-accelerating, and self-healing properties, Airy plasmons show promise for use in the trapping, transporting, and sorting of micro-objects, imaging, and chip scale signal processing. However, high dissipative loss and lack of dynamical steerability restrict the implementation of Airy plasmons in these applications. Here we reveal hybrid Airy plasmons for the first time by taking a hybrid graphene-based plasmonic waveguide in the terahertz (THz) domain as an example. Due to coupling between optical modes and plasmonic modes, the hybrid Airy plasmons can have large propagation lengths and effective transverse deflections, where the transverse waveguide confinements are governed by the hybrid modes with moderate quality factors. Meanwhile, the propagation trajectories of the hybrid Airy plasmons are dynamically steerable by changing the chemical potential of graphene. These hybrid Airy plasmons may promote the further discovery of non-diffracting beams along with the emerging developments of optical tweezers and tractor beams.

A CPS framework based perturbation constrained buffer planning approach in VLSI design

As VLSI technology advances towards nanoscale devices, interconnect delay is becoming increasingly important, and could be effectively reduced using buffer insertion. The widely-used buffer insertion technique in industry is to insert a set of buffers on the chip, which may overlap some gates, and then greedily move the buffers to the nearest available buffer holes. The moving distance of inserted buffers largely affects the wirelength which may result in the increase of the interconnect delay. This necessitates efficient algorithms to minimize the moving distance of buffers for effective buffer insertion to obtain high-performance VLSI designs.This paper proposes an efficient, perturbation constrained buffer planning algorithm to maximize the candidate buffer holes with regarding to the feature of CPS based buffering design framework. Instead of directly moving buffers to the existing available buffer holes, the proposed algorithm changes the original placement by moving some gates tinily to provide more flexibility for buffer insertion. The integer linear programming based technique is designed for the physical design flow which allows small moving range of gates. Parallel technique is utilized to solve the ILP problems efficiently when the scale of chip is increasing. Experimental results have shown that the proposed algorithm achieves at most 41.49% increase in the available buffer holes when compared to the algorithm with no gate movement.

Dielectric Metasurface as a Platform for Spatial Mode Conversion in Nanoscale Waveguides.

We experimentally demonstrate a nanoscale mode converter that performs coupling between the first two transverse electric-like modes of a silicon-on-insulator waveguide. The device operates by introducing a nanoscale periodic perturbation in its effective refractive index along the propagation direction and a graded effective index profile along its transverse direction. The periodic perturbation provides phase matching between the modes, while the graded index profile, which is realized by the implementation of nanoscale dielectric metasurface consisting of silicon features that are etched into the waveguide taking advantage of the effective medium concept, provides the overlap between the modes. Following the device design and numerical analysis using three-dimensional finite difference time domain simulations, we have fabricated the device and characterized it by directly measuring the modal content using optical imaging microscopy. From these measurements, the mode purity is estimated to be 95% and the transmission relative to an unperturbed strip waveguide is as high as 88%. Finally, we extend this approach to accommodate for the coupling between photonic and plasmonic modes. Specifically, we design and numerically demonstrate photonic to plasmonic mode conversion in a hybrid waveguide in which photonic and surface plasmon polariton modes can be guided in the silicon core and in the silicon/metal interface, respectively. The same method can also be used for coupling between symmetric and antisymmetric plasmonic modes in metal-insulator-metal or insulator-metal-insulator structures. On the basis of the current demonstration, we believe that such nanoscale dielectric metasurface-based mode converters can now be realized and become an important building block in future nanoscale photonic and plasmonic devices. Furthermore, the demonstrated platform can be used for the implementation of other chip scale components such as splitters, combiners couplers, and more.

Enhanced light‐vapor interactions and all optical switching in a chip scale micro‐ring resonator coupled with atomic vapor

AbstractThe coupling of atomic and photonic resonances serves as an important tool for enhancing light‐matter interactions and enables the observation of multitude of fascinating and fundamental phenomena. Here, by exploiting the platform of atomic‐cladding wave guides, the resonant coupling of rubidium vapor and an atomic cladding micro ring resonator is experimentally demonstrated. Specifically, cavity‐atom coupling in the form of Fano resonances having a distinct dependency on the relative frequency detuning between the photonic and the atomic resonances is observed. Moreover, significant enhancement of the efficiency of all optical switching in the V‐type pump‐probe scheme is demonstrated. The coupled system of micro‐ring resonator and atomic vapor is a promising building block for a variety of light vapor experiments, as it offers a very small footprint, high degree of integration and extremely strong confinement of light and vapor. As such it may be used for important applications, such as all optical switching, dispersion engineering (e.g. slow and fast light) and metrology, as well as for the observation of important effects such as strong coupling, and Purcell enhancement. image

Microresonator soliton dual-comb spectroscopy.

Measurement of optical and vibrational spectra with high resolution provides a way to identify chemical species in cluttered environments and is of general importance in many fields. Dual-comb spectroscopy has emerged as a powerful approach for acquiring nearly instantaneous Raman and optical spectra with unprecedented resolution. Spectra are generated directly in the electrical domain, without the need for bulky mechanical spectrometers. We demonstrate a miniature soliton-based dual-comb system that can potentially transfer the approach to a chip platform. These devices achieve high-coherence pulsed mode locking. They also feature broad, reproducible spectral envelopes, an essential feature for dual-comb spectroscopy. Our work shows the potential for integrated spectroscopy with high signal-to-noise ratios and fast acquisition rates.

Autonomous underwater vehicle navigation using a single tomographic node

This study investigates AUV navigation using the one-way travel-time from an ocean tomographic sensor node. For the study of ocean acoustic tomography, several tomographic nodes are moored in the study area and broadcast m-sequence signals periodically. Each moored node consists of an acoustic transceiver, a GPS module, and a processing unit. The pulse-per-second signal from the GPS module is used to ensure the time synchronization of all the moored nodes. A tomographic sensor is installed on an AUV, serving as a moving node. To obtain highly accurate one-way travel-time between moored nodes and AUV, a chip scale atomic clock is operated on the AUV. Based on dead-reckoning and travel-time measurement, Extended Kalman Filter (EKF) is employed to improve the AUV localization. An experiment was conducted using an AUV and one moored node deployed in a shallow water environment southwest of Taiwan. The measurements from a Doppler velocity logger and a compass are used to calculate the current position of vehicle. The AUV was operated near the surface to obtain the GPS position as the ground truth for the performance evaluation. Preliminary results show the RMS position error between the EKF prediction and ground truth is about 80 m.

Advanced Wafer Level Packaging of RF-MEMS with RDL Inductor

Abstract The market for portable and mobile data access devices that are wirelessly connected to the cloud anytime and anywhere is exploding. The trend to access any network from anywhere is driving increased functional convergence in the radio, which translates into increased packaging complexity and sophistication. This is creating unprecedented demand for RF components providing more integration- in smaller package sizes. There are exciting interconnect technologies in wafer level packaging such as wafer level chip scale packaging (WLCSP) or fan-out wafer level packaging (FO-WLP) solutions such as embedded Wafer Level Ball Grid Array (eWLB) to meet these needs. One of the most promising solutions to enable the required RF performance levels in mobile and wearable devices is the use of RF MEMS Tuners. Mobile original equipment manufacturers (OEMs) are rapidly adopting antenna tuning solutions to be able to provide the required signal strength across the large number of LTE spectrum bands used globally. With RF MEMS technology now maturing, the biggest challenge to address the fast growing opportunity was to find a suitable packaging technology that can deliver RF MEMS tuners in the smallest possible form factor, while maintaining the excellent performance characteristics of the RF MEMS technology. After careful analysis, an eWLB/FO-WLP package was adopted and released to volume production in 2015. The commercial eWLB/FO-WLP RF MEMS tuners outperform traditional RF silicon-on-insulator (SOI) switch-based antenna tuning solutions, resulting in much higher data rates (up to 2×) and improved battery life (up to 40%). Redistribution layers (RDL) in eWLB are utilized for higher electrical performance and complex routing to meet electrical requirements. The ability to utilize embedded passives in a multi-layer eWLB structure provides a number of advantages including cost reduction, footprint reduction and increased reliability. Inductors in eWLB offer significantly better performance compared to inductors in standard on-chip technologies. In this paper, we examine the WLCSP and eWLB packaging assembly flow, solutions to RF design challenges as well as characterization of RF performance. Further improvement of the quality factor of the integrated inductor and capacitors by using low-loss thin-film dielectrics and molding compound in eWLB will be reported as well. Package level reliability test results will also be presented in this paper.

High Speed Fluorescent Inspection of Non-visible defects

Abstract The semiconductor industry continues to drive down defectivity rates, especially as the liability to ship replacement parts for field failures is pushed back into the supply chain. As dimensions are driven down to finer pitch, there are a certain class of defects that are caused by organic residue. Inspection using white light for advanced packaging is well known. However, organic residue defects appear transparent to white light but can be the root cause of field reliability issues. Residue on top of a bump, as an example, could cause damage to the part when operating at high temperatures in the field. Up until now, such an inspection would have been performed either using a manual fluorescent microscope or not at all. A well understood capability gap in the industry, defects due to organic residue are present in copper pillar bump and wafer level chip scale packages – both fan-in and fan-out, as well as packages based on organic substrate. This paper presents data from high-speed fluorescent inspection that could address this problem in a unique way that was not possible up until now.

Nyquist pulse shaping using arrayed waveguide grating routers.

We propose and demonstrate by simulations a novel Nyquist-WDM (N-WDM) superchannel transmitter based on an arrayed waveguide grating router (AWGR). This approach can generate Nyquist pulses at multiple wavelengths using a single AWGR. Results for a 3-channel 960-Gbit/s QPSK superchannel system show that a 10% guard band reduces the inter-channel interference (ICI) sufficiently. The design introduces less than 0.16-dB penalty when the waveguide loss is 2 dB/cm and 0.73-dB penalty when the standard deviation of phase error is 10°. Such Nyquist pulse shapers can be realised on a chip scale using photonic integrated circuits technology, and could be compactly integrated with other functional components to create single-chip N-WDM superchannel transmitters.

On-chip multi spectral frequency standard replication by stabilizing a microring resonator to a molecular line

Stabilized laser lines are highly desired for myriad of applications ranging from precise measurements to optical communications. While stabilization can be obtained by using molecular or atomic absorption references, these are limited to specific frequencies. On the other hand, resonators can be used as wide band frequency references. Unfortunately, such resonators are unstable and inaccurate. Here, we propose and experimentally demonstrate a chip-scale multispectral frequency standard replication operating in the spectral range of the near IR. This is obtained by frequency locking a microring resonator (MRR) to an acetylene absorption line. The MRR consists of a Si3N4 waveguides with microheater on top of it. The thermo-optic effect is utilized to lock one of the MRR resonances to an acetylene line. This locked MRR is then used to stabilize other laser sources at 980 nm and 1550 nm wavelength. By beating the stabilized laser to another stabilized laser, we obtained frequency instability floor of 4×10−9 at around 100 s in terms of Allan deviation. Such stable and accurate chip scale sources are expected to serve as important building block in diverse fields such as communication and metrology.

On Frequency Combs in Monolithic Resonators

Abstract Optical frequency combs have become indispensable in astronomical measurements, biological fingerprinting, optical metrology, and radio frequency photonic signal generation. Recently demonstrated microring resonator-based Kerr frequency combs point the way towards chip scale optical frequency comb generator retaining major properties of the lab scale devices. This technique is promising for integrated miniature radiofrequency and microwave sources, atomic clocks, optical references and femtosecond pulse generators. Here we present Kerr frequency comb development in a historical perspective emphasizing its similarities and differences with other physical phenomena. We elucidate fundamental principles and describe practical implementations of Kerr comb oscillators, highlighting associated solved and unsolved problems.

Drop failure modes of Sn–3.0Ag–0.5Cu solder joints in wafer level chip scale package

To reveal the drop failure modes of the wafer level chip scale packages (WLCSPs) with Sn–3.0Ag–0.5Cu solder joints, board level drop tests were performed according to the JEDEC standard. Six failure modes were identified, i.e., short FR-4 cracks and complete FR-4 cracks at the printing circuit board (PCB) side, split between redistribution layer (RDL) and Cu under bump metallization (UBM), RDL fracture, bulk cracks and partial bulk and intermetallic compound (IMC) cracks at the chip side. For the outmost solder joints, complete FR-4 cracks tended to occur, due to large deformation of PCB and low strength of FR-4 dielectric layer. The formation of complete FR-4 cracks largely absorbed the impact energy, resulting in the absence of other failure modes. For the inner solder joints, the absorption of impact energy by the short FR-4 cracks was limited, resulting in other failure modes at the chip side.