Wafer Level Packaging Research Articles

In-Place Evaluation of Powering and Signaling Within Fan-Out Multiple IC Chip Packaging

This article confirms the advantage of fan-out (FO) packaging in the electrical performance of power delivery among integrated circuit (IC) chips with the best use of land side capacitors (LSCs). On-chip in-place waveform measurements quantitatively evaluate the integrity of powering and signaling within FO wafer level packaging (FOWLP) multiple chip module (MCM) demonstrators, where a pair of IC chips are assembled with LSCs with different sizes and structures. The IC chip incorporates an array of 12 digital cores and on-chip waveform monitor (OCM) circuits. Each digital core consists of a low-voltage differential signaling (LVDS) transceiver channel that is backed by a static random access memory (SRAM)-based built-in self test (BIST) module and supplied by an on-chip voltage regulator module (VRM). The LSCs are placed on the bottom side of an FO interposer and inserted between the output of VRM and the ground plane almost ideally with the shortest length of physical traces. A Si membrane capacitor of 10 nF sustains the lowest power line impedance over the frequency range of 2.0 GHz more constantly than a multilayer ceramic counterpart, and attenuates the high-order harmonic frequency components to the clocking frequency at 750 MHz. The leverage of LSCs in powering also improves signaling and helps achieve the wider eye openings in LVDS channels. The implications are elaborated for the capacitor selections with respect to the physical types of capacitors, the size of capacitances, and the level of shares in power delivery among digital cores, all toward the higher level of integrity in powering and signaling in FOWLP MCMs.

HRXRD and micro-CT multiscale investigation of stress and defects induced by a novel packaging design for MEMS sensors

Advanced methods such as high-resolution X-ray diffraction and X-ray micro CT allow highly precise determination of materials' residual stress, volume, and lattice defects. Their conjoint exploitation offers a powering tool to facilitate the industrial implementation of novelties in microfabrication. The wafer-level packaging represents a critical step of the MEMS microfabrication resulting in a hermetic, defect- and stress-free interface. For the first time, such critical parameters are investigated related to a novel wafer-bonding process, namely Impulse Current Bonding (ICB), and compared to the standard anodic bonding technology used for MEMS production. The ICB does not induce any relevant residual stress at the interface above the limit of 1 MPa, determined by the unrivaled strain detectability of HRXRD. The bonding interface is devoid of any defects, as defined by X-ray micro-CT studies.The ICB technology reduces the thermal budget of the packaging up to 85% compared to the anodic bonding, which outlines an outstanding step forward in reducing the energy footprint. The extension of ICB to other materials systems such as glass to ceramic or metals makes this technology a promising candidate for numerous applications, including the design of biocompatible devices for bio-implants.

Design for the Package-Board Transition and Its Testability Design in the Fan-Out Wafer-Level Package

A fan-out wafer level package (FOWLP) with double-sided four redistribution layers (RDLs) and the mega pillars connecting the front and back RDLs has been proposed for millimeter-wave applications. A well-matched package-board transition has been designed in this paper. The simulated insertion loss for the transition is about 0.82 dB at 79 GHz, and the simulated return loss is better than 10 dB from 72 GHz to 86 GHz. More importantly, two different measurement methods based on the port reduction technique and the Thru-Reflect-Line (TRL) calibration technique have been proposed to get the S parameters of the transition. Moreover, the feasibility of the two methods has been verified by simulation.

Experimental and simulative study of warpage behavior for fan-out wafer-level packaging

Controlling warpage effects in fan-outwafer-level packaging (FO-WLP) is of key importance for realizing reliable and cost-efficient system in packages (SiPs). However, warpage effects can occur during the manufacturing process, caused by a combination of different processing temperatures, different materials, and the changing properties of the materials (e.g. polymerization and related cure shrinkage). One approach to controlling warpage could be realized by assessing a numerical simulation workflow of the FO-WLP process chain, in which the relevant material properties and geometry are used as input. Since there are many different steps included in the FO-WLP process, accompanied by complex material behavior, this workflow is not straight-forward. In the present paper, the first FO-WLP processing steps are investigated in detail by performing extensive thermo-mechanical material characterization, temperature-dependent warpage measurements, and numerical simulations. The investigation focuses on two epoxy mold compound (EMC) materials with completely different physical properties.The warpage measurements of bi-material (EMC and silicon) samples reveal an irreversible effect after passing certain processing temperatures, which are significant for final warpage at room temperature. A new approach to measuring the coefficient of thermal expansion (CTE) is discussed, using a temperature profile based on the temperature in the process, instead of the three identical temperature ramps suggested by the typical standards. This new approach makes it possible to determine possible shrinkage effects. Within the simulation model, the hysteresis effect observed in the experiment is taken into account by adding a shrinkage strain as well as changing the CTE values during the process. A very good agreement between the experiment and simulation is achieved, which is shown for several demonstrators with different epoxy mold compound materials and thicknesses.

Economic and embodied energy analysis of integrated circuit manufacturing processes

Integrated circuits (ICs) are the fundamental microelectronic building blocks of typical information and communication technology (ICT) devices such as laptops and smartphone. With the emergence of faster and cheaper low-power ICs for the growing ICT market, there is a limited information on their manufacturing energy and economic impacts owing to the lack of recurrent upgradation of proprietary IC manufacturing process data. Economic and life cycle energy assessments (LCAs) of IC manufacturing and assembly processes were conducted using the latest bill of materials (BOM) manufacturing data in a state-of-the-art IC manufacturing cost software tool developed by IC Knowledge, LLC. IC manufacturing cost was estimated to be $1.00-$5.00/cm2; the high-end cost represents the most advanced 3D NAND IC technology with the Wafer Level Chip Scale Package cost of $4/cm2. Total cumulative energy demand (CED) estimates of IC manufacturing using the OpenLCA software ranged from 9 to 38 MJ/cm2 or 56–235 BJ/month with the largest share (~ 75%) from on-site energy. The IC manufacturing CED is projected to increase with the progress in IC technology node, which has increased by more than two times for technology node evolution from 110 to 14 nm. Furthermore, the representative detailed BOM data were considered to reduce the CED uncertainties of the estimated standard deviation of 35%− 42%.

A 1.9-dB NF K-Band Temperature-Healing Phased-Array Receiver Employing Hybrid Packaged 65-nm CMOS Beamformer and 0.1-μm GaAs LNAs

A 1.9-dB NF K-band phased-array receiver (RX) is presented, which employs the hybrid packaged 65-nm CMOS beamformer and 0.1- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> GaAs LNAs based on the fan-out wafer-level chip-scale packaging (WLCSP) technology. Power-efficient gain and phase tuning blocks are utilized to reduce power consumption. Temperature-healing design methodology is adopted to ensure nearly constant gain response versus temperature variations. The proposed phased-array RX only consumes 30.2-mW dc power per channel and achieves < 1.2-dB gain variation and < 0.9-dB NF variation from −40 °C to 85 °C.

Predicting Wafer-Level Package Reliability Life Using Mixed Supervised and Unsupervised Machine Learning Algorithms.

With the increasing demand for electronic products, the electronic package gradually developed toward miniaturization and high density. The most significant advantage of the Wafer-Level Package (WLP) is that it can effectively reduce the volume and footprint area of the package. An important issue in the design of WLP is how to quickly and accurately predict the reliability life under the accelerated thermal cycling test (ATCT). If the simulation approach is not adopted, it usually takes several ACTCs to design a WLP, and each ACTC will take several months to get the reliability life results, which increases development time considerably. However, simulation results may differ depending on the designer’s domain knowledge, ability, and experience. This shortcoming can be overcome with artificial intelligence (AI). In this study, finite element analysis (FEA) is combined with machine learning algorithms, e.g., Kernel Ridge Regression (KRR), to create an AI model for predicting the reliability life of electronic packaging. Kernel Ridge Regression (KRR) combined with the K-means cluster algorithm provides a highly accurate and efficient way to obtain AI models for large-scale data sets.

Experimental and Numerical Investigations of the Warpage of Fan-Out Wafer-Level Packaging With SAW Filters

Fan-out wafer-level package (FOWLP) technology is an ideal scheme for the surface acoustic wave (SAW) filter packaging due to its potential to achieve extensive numbers of interconnects with standard pitches at any shrink pattern of the wafer. Nevertheless, predicting the wafer warpage in the processes timeline is an intractable but instructive issue. This article focuses on the evolution of the wafer warpage in different packaging processes and on ameliorating the warpage control scheme for the FOWLP with the (SAW) filters. Combined with the meso-mechanical model and the transversely isotropic model (TIM) of composite material, curing deformation is taken into account. Given the anisotropy coefficient thermal expansion (CTE) of the LiTaO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> , experiments and simulations are performed to analyze the influence of the process, structure, and material effects on the warpage. In addition, a new experimental process is proposed to reduce the impact of significant mismatches with submillimeter dies. Compared with the theoretical simulations, a class of warpage tests performed are achieved consensus. Finally, the warpage of the 8-in wafer is controlled within 2 mm.

Board Level Reliability of Automotive Grade WLCSP for Radar Applications

Wafer-Level Chip Scale Packages (WLCSPs) are becoming commonplace in the industry due to their small form factor. Applications include industrial and automotive which demand high reliability performance. Additionally, WLCSPs may be superior in some implementations to other package options for RF performance in the mmWave spectrum, which is desired for automotive radar application. But board level reliability can be a challenge for some WLCSP package due to CTE mismatch between Si and PCB. Variety of factors including PCB materials, sphere alloys, and board level underfills can influence the board level reliability of WLCSP packages. In this study the industry’s first auto grade 1 capable large WLCSP package. (~ 72 mm2 body size, 18x15 BGA array, 0.5 mm pitch) is presented. Board level underfill application was utilized to achieve automotive grade board level reliability. Underfills are typically selected based on thermomechanical properties of unaged materials. An understanding of the evolution of underfill material properties under thermal aging is important for selecting a stable material capable of meeting the reliability requirements.&#x0D; This study evaluates board level underfills and edge bond materials in the form of stand-alone samples and applied to a large daisy-chain WLCSP. The underfilled daisy-chain WLCSPs and the stand-alone samples are placed in a ‑40/125C air cycling chamber (1 cycle/hour). Glass transition temperature (Tg), elastic modulus (E), and coefficient of thermal expansion (CTE) are measured using Dynamic Mechanical Analysis (DMA) and Thermomechanical Analysis (TMA) on the stand-alone samples at various intervals to monitor the evolution of material properties. Simultaneously, the underfilled daisy chain WLCSPs are monitored electrically using an event detector. The combination of material property measurements and cycles to electrical failure can be used to correlate underfill material properties and WLCSP board-level reliability. The results of this study can provide material property guidance for underfill selection.

Wafer-Level Assembly of Physics Package for Chip-Scale Atomic Clocks

Chip-scale atomic clocks (CSACs) have been extensively investigated and many prototypes or products have been realized as time sensors. Researchers focus on improving the frequency stability performance, reducing the volume and the power consumption of CSACs. To the best of our knowledge, the physics packages reported until now are all assembled from discrete components. This traditional assembly method has a very low efficiency and causes variations among different physics packages. In this article, we propose a wafer-level assembled physics package for CSACs based on three dimensional (3-D) wafer-level packaging (WLP) and microelectromechanical system (MEMS) technologies. The components of the physics package are all fabricated on wafers. These wafers are integrated together vertically and then diced into separate physics packages. The proposed method has the advantages of high uniformity among different physics packages and high efficiency. And it improves the utilization rate of wafers by reducing the unused area. Thus, the production cost is reduced considerably. The volume of the proposed functional physics package is less than 8 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> . The prototype chip-scale atomic clock incorporating the proposed physics package reveals the coherent population trapping (CPT) linewidth of 1.8 kHz and the total power consumption of about 20mW. The frequency stability is about <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$6.1 \times 10^{-12}$ </tex-math></inline-formula> @1000s. The observed results demonstrate promising performance of the wafer-level assembled physics package. The approach described in this article reveals a viable method for batch production for its low cost, high efficiency and high product uniformity.

Study of Bondable Laser Release Material Using 355 nm Energy to Facilitate RDL-First and Die-First Fan-Out Wafer-Level Packaging (FOWLP)

A thorough evaluation on selecting a bondable laser release material for redistribution layer (RDL)-first and die-first fan-out wafer-level packaging (FOWLP) is presented in this article. Four laser release materials were identified based on their absorption coefficient at 355 nm. In addition, all four of these materials possess thermal stability above 350 &#x00B0;C and pull-off adhesion on a Ti/Cu layer greater than 8 psi, further illustrating their compatibility in FOWLP. To further evaluate these materials, focus ion beam (FIB) inspection was used to examine the profile of a single-pulse laser ablation region, ensuring free penetration of 355-nm laser energy. With a designated die bonding test vehicle, die shift less than 1.5 <inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> and rotation less than 0.02&#x00B0; before and after molding was achieved with the material bondable at temperatures lower than 200 &#x00B0;C. Furthermore, this same material required a laser energy of less than 3 W for laser release. A bondable laser release material that eliminates the requirement for a die attach material from the traditional process flow facilitates the development of cost-effective FOWLP.

Study of shear locking effect on 3D solder joint reliability analysis

Abstract The fabrication process of WLP (wafer-level packaging) has become more mature, and using the finite element method (FEM) to predict the reliability life of electronic packaging can shorten the WLP design cycles. This study adopted the NSMD (non-solder mask defined) solder joint structure in WLP and used an energy method to predict the solder joint geometry. A fixed mesh size will be determined for the critical region of the solder joint to evaluate the inelastic strain due to the thermal loading in finite element analysis. However, under the influence of the solder geometry of some tested vehicles, especially when the solder contact angle of the lower pad is less than 20 degrees, a shear locking phenomenon will occur at the solder joint. This phenomenon causes abnormal energy transfer. The excessive strain is concentrated on the upper part of the solder joint, resulting in an incorrect estimation of reliability life. Reduced integration can prevent shear locking and has improved strain results compared to full integration. The results of this research demonstrate that the FEM using proper mesh size control and the reduced integration point element in critical regions can deliver accurate reliability life prediction for WLP.

Development of 3D Wafer Level Hermetic Packaging with Through Glass Vias (TGVs) and Transient Liquid Phase Bonding Technology for RF Filter.

The development of 5G mobile communication created the need for high-frequency communication systems, which require vast quantities of radio frequency (RF) filters with a high-quality factor (Q) and low inband losses. In this study, the packaging of an RF filter with a through-glass via (TGV) interposer was designed and fabricated using a three-dimensional wafer-level package (3D WLP). TGV fabrication is a high-yielding process, which can produce high precision vias without masking and lithography and reduce the manufacturing cost compared with the through silicon via (TSV) solution. The glass interposer capping wafer contains Cu-filled TGV, a metal redistribution layer (RDL), and the bonding layer. The RF filter substrate with Au bump is bonded to the capping wafer based on Au-Sn transient liquid phase (TLP) bonding at 280 °C with a 40 kN (approximately 6.5 MPa) bonding force. Experimental results show that shear strengths of approx. 54.5 MPa can be obtained, higher than the standard requirement (~6 MPa). In addition, a comparison of the electrical performance of the RF filter package after the pre-conditional level three (Pre-Con L3) and unbiased highly accelerated stress (uHAST) tests showed no difference in insertion attenuation across the passband (<0.2 dB, standard value: <1 dB). The final packages passed the reliability tests in the field of consumer electronics. The proposed RF filter WLP achieves high performance, low cost, and superior reliability.

Influence of Process Parameters on Surface Activated Aluminum-to-Aluminum Wafer Bonding

Aluminum-to-aluminum wafer bonding is a promising technique for future wafer-level packaging and heterogeneous integration. The main challenge for a successful Al-to-Al thermocompression bonding is the fast oxidation of the aluminum surface. In this article, a surface-activated Al-to-Al wafer bonding process for patterned 200-mm wafers is presented, which removes the oxide in an argon plasma and enables a high bond quality with an accurate alignment. The influence of the bonding parameters’ temperature (200 °C–300 °C), force (20–40 kN), and activation time (2.5–5 min) on the contact resistances and bonding yield is analyzed. Additionally, we modified an etch mask during wafer fabrication and thereby improved the condition of the Al pad surface, which resulted in a higher bonding quality. Based on this optimized wafer fabrication process, we achieved a high bonding yield of >85% and contact resistances in the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{m}\Omega $ </tex-math></inline-formula> range for bonding temperatures as low as 250 °C. This demonstrates the potential of Al-to-Al wafer bonding to create reliable interconnects for 3-D wafer-level integration.

Investigation of Warpage for Multi-Die Fan-Out Wafer-Level Packaging Process.

This paper focuses on characterizing the evolution of warpage, effects of epoxy molding compound (EMC), and effects of carrier 2 (the second carrier in the process) of 12 inch RDL-first multi-die fan-out wafer-level packaging (FOWLP) during the manufacturing process. The linear viscoelasticity properties of EMC and polyimide (PI) were characterized using dynamic mechanical analysis (DMA) in the frequency domain at different temperatures., The elastic and viscoelastic model were used for PI and EMC, the finite element analyses (FEA) of the cured structure were carried out and the results were compared with the test results. The viscoelastic properties of the EMC in the FEA could predict the wafer warpage more accurately. The FEA and experiments were used to investigate the evolution of warpage. The molding had a great influence on the warpage. The effects of the EMC and carrier 2 were also investigated with FEA. The wafer warpage could be reduced by lowering the thickness of the EMC, increasing the thickness of carrier 2, and selecting EMC and carrier 2 with a matched coefficient of thermal expansion (CTE).

Recent Advances and Trends in Advanced Packaging

In this study, advanced packaging is defined. The kinds of advanced packaging are ranked based on their interconnect density and electrical performance, and are grouped into 2-D, 2.1-D, 2.3-D, 2.5-D, and 3-D IC integration, which will be presented and discussed. Chiplet design and heterogeneous integration packaging provide alternatives to the system on chips (especially for advanced nodes) will be discussed. Different substrates, such as size, pin-count, and metal linewidth and spacing for advanced packaging, are examined. The lateral communication between chiplets, such as the silicon bridges embedded in organic build-up package substrate and fan-out epoxy molding compound, as well as flexible bridges, will be presented. Fan-in packaging, such as the six-side molded wafer-level chip-scale package (WLCSP) and its comparison with the ordinary WLCSP, are presented. Fan-out packaging, such as the chip-first with die face-up, chip-first with die face-down, and chip-last and their difference, will be provided. Low-loss dielectric materials for high-speed and high-frequency applications in advanced packaging will be presented. Flip-chip assembly by mass reflow, thermocompression bonding, and bumpless hybrid bonding will be briefly mentioned first.

Development of 3-D Wafer Level Packaging for SAW Filters Using Thin Glass Capping Technology

The introduction of 5G mobile communication created the need to support a large number of radio frequency (RF) bands. This required high performance and reduced size for microacoustic filters. Based on these requirements, a new three-dimensional wafer-level packaging (3-D WLP) solution based on the predecessors’ developed technology was presented to resolve reliability issues for surface acoustic wave (SAW) filter packages with large cavities. In the 3-D WLP, vertical interconnects were realized using through glass vias (TGVs). To enable such a process scheme, thin glass caps with TGVs were formed through laser-induced chemical etching. Then, glass capping dies were bonded on the corresponding LiTaO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> (LT) device wafer to generate a cavity structure. Partial filling of the vias on the pad was used, and a metal trace was formed on the glass. Ball grid arrays (BGAs) were formed on top of the glass. Finally, an SAW filter WLP was fabricated. This glass capping packaging avoids the outgassing problem of conventional thin-film acoustic packaging at high temperatures, which would cause the contamination of the interdigital transducers (IDTs). In addition, a numerical study based on the 3-D finite element (FE) model has been conducted to analyze the reliability of the package. The built model was applied to perform parametric studies on the effects of package geometry, material properties, and the processing conditions on reliability. Based on the above studies, the optimized SAW filter WLP successfully passed the reliability test of pre-con level 3 and temperature cycling test (TCT, −40 °C ~ 125 °C).

Selection and Characterization of Photosensitive Polyimide for Fan-Out Wafer-Level Packaging

Fan-out wafer-level packaging (FOWLP) is one of the most popular microelectronics packaging technologies. Redistribution layers (RDLs) are employed to expand chip pads beyond the chip edges. Photosensitive polyimide (PI) is widely used in RDLs fabrication. But it also introduces some issues during the thermal cycling test or highly accelerated stress test, for example, warpage, peeling, blistering, and even cracking. In order to reduce these risks at the materials selecting stage, four common dielectric materials–PI A, B, C, and phenolic resin D were investigated in their thermomechanical properties and surface characteristics. And a design of the experiment on process improvement was conducted. The experimental results show that material A owning excellent elongation exceeding 30%, acceptable curing temperature below 260 °C, and low coefficient of thermal expansion (CTE) at 52 ppm/K is more suitable to be adapted as dielectric in RDLs compared with other materials chosen in this article.

Application of the surface planer process to Cu pillars and wafer support tape for high-coplanarity wafer-level packaging

Application of the surface planer process to Cu pillars and wafer support tape for high-coplanarity wafer-level packaging

Low-temperature curable and low-dielectric polyimide nanocomposites using aminoquinoline-functionalized graphene oxide Nanosheets

Low-temperature curable and low-dielectric polyimides (PIs) are required in wafer-level packaging (WLP) which is an advanced microelectronic packaging technology. Herein, a low-cost and multifunctional nanofiller (aminoquinoline-functionalized graphene oxide , AQL-GO) is synthesized, which ingeniously achieved the above-mentioned requirements of polyimide nanocomposites by nucleophilic attack of QL and chaotic packing of the polymer chain. The results show that the nanocomposite can be fully cured at only 200 °C and have a low dielectric constant ( 2.96@1 MHz) with 0.5 wt% addition of AQL-GO. Furthermore, the mechanical and thermal properties of all nanocomposites cured at 200 °C (the elongation at break can reach 39.69%, the Young's modulus can reach 2.38 GPa and T 5% can reach 530.55 °C) are almost equal or even better than those of pure PI cured at 350 °C. Therefore, the PI/AQL-GO nanocomposites have industrial prospects in advanced microelectronic packaging. Low-temperature curing (200 °C) and low-dielectric (2.96@1 MHz) polyimide/aminoquinoline-functionalized graphene oxide (PI/AQL-GO) nanocomposites have been synthesized for next-generation microelectronic packaging. • Polyimide/aminoquinoline-functionalized graphene oxide (PI/AQL-GO) nanocomposites were successfully synthesized. • The nanocomposites can be fully cured at 200 °C and possess low dielectric constant (2.96@1 MHz). • The nanocomposites also possess excellent mechanical and thermal properties. • In situ grafting process was proposed to explain the mechanism.