Chip Scale Package Assemblies Research Articles

Thermal and Reliability Demonstration of a Large Die on a Low CTE Chip Scale Package

In organic packages, large die and large laminate body sizes are susceptible to CTE (coefficient of thermal expansion) mismatch driven warpage, stresses and strains, which can result in C4 white bumps, micro Ball Grid Array (BGA) interconnection issues, and package thermal reliability concerns. Low CTE carriers minimize these concerns and allow increased chip join yields and improved package reliability. Modeling and characterization of warpage, chip and micro BGA integrity and electrical characterization of a low CTE, Chip Scale Package (CSP) were described in an earlier paper. In this paper we report the progress on the next phase - thermal and chip package interaction (CPI) evaluation of a single chip CSP designed for use with Multi-Chip Modules (MCM). Assembly, characterization, thermal performance and reliability stress results of these low CTE CSP Single Chip Modules (SCMs) are described. Measured warpage values are compared with thermo-mechanical modeling results. Demonstration of a dual CSP design and assembly with large dies is also presented. The successful demonstration of the material set, bond and assembly processes, and reliability of a large die, high I/O CSP, followed by the demonstration of a dual CSP on a multi component carrier, are fore-runners to the development of multi-CSP MCMs.

Dynamic reliability approach of chip scale package assembly under vibration environment

Purpose – The purpose of this paper is to perform experimental tests on fatigue characteristics of chip scale package (CSP) assembly under vibration. Some suggestions for design to prolong fatigue life of CSP assembly are provided. Design/methodology/approach – The CSP assembly which contains different package structure modes and chip positions was manufactured. The fatigue characteristics of CSP assembly under vibration were tested. The fatigue load spectrum of CSP assembly was developed under different excitation. The fatigue life of chips can be estimated by using the high-cycle fatigue life formula based on different stress conditions. The signal–noise curve shows the relationship between fatigue life and key factors. The design strategy for improving the fatigue life of CSP assembly was discussed. Findings – The CSP chip has longer fatigue life than the ball grid array chip under high cyclic strain. The closer to fixed point the CSP chip, the longer fatigue life chips will have. The chip at the edge of the printed circuit board (PCB) has longer fatigue life than the one in the middle of the PCB. The greater the excitation imposed on the assembly, the shorter the fatigue life of chip. Research limitations/implications – It is very difficult to set up a numerical approach to illustrate the validity of the testing approach because of the complex loading modes and the complex structure of CSP assembly. The research on an accurate mathematical model of the CSP assembly prototype is a future work. Practical implications – It builds a basis for high reliability design of high-density CSP assembly for engineering application. In addition, vibration fatigue life prediction method of chip-corner solder balls is deduced based on three-band technology and cumulative damage theory under random vibration so as to verify the accuracy of experimental data. Originality/value – This paper fulfils useful information about the dynamic reliability of CSP assembly with different structural characteristics and material parameters.

Board-Level Solder Joint Reliability of Edge- and Corner-Bonded Lead-Free Chip Scale Package Assemblies Subjected to Thermal Cycling

In this paper, we present the results of thermal cycling test for edge- and corner-bonded lead-free chip scale packages (CSPs), which was carried out on the basis of the IPC-9701 test standard. Six materials were used in this study: four edge-bond adhesives and two corner-bond adhesives. These adhesives were compared with CSPs with full capillary flow underfill (FCFU) and without adhesives. The thermal cycling test results show that corner-bond adhesive has comparable solder joint reliability performance with CSP without adhesive, and is better than edge-bond adhesive, followed by CSPs with FCFU. In addition, the adhesives with a low coefficient of thermal expansion, a high glass transition temperature and a intermediate storage modulus yielded good performance. Results of detailed failure analysis indicate that the dominant failure mode is solder bulk fatigue cracking near package and/or printed circuit board (PCB) pads, and that the location of critical solder joints change from die edges to package corners with the introduction of adhesives.

Board-Level Solder Joint Reliability of Edge- and Corner-Bonded Lead-Free Chip Scale Package Assemblies Subjected to Thermal Cycling

In this paper, we present the results of thermal cycling test for edge- and corner-bonded lead-free chip scale packages (CSPs), which was carried out on the basis of the IPC-9701 test standard. Six materials were used in this study: four edge-bond adhesives and two corner-bond adhesives. These adhesives were compared with CSPs with full capillary flow underfill (FCFU) and without adhesives. The thermal cycling test results show that corner-bond adhesive has comparable solder joint reliability performance with CSP without adhesive, and is better than edge-bond adhesive, followed by CSPs with FCFU. In addition, the adhesives with a low coefficient of thermal expansion, a high glass transition temperature and a intermediate storage modulus yielded good performance. Results of detailed failure analysis indicate that the dominant failure mode is solder bulk fatigue cracking near package and/or printed circuit board (PCB) pads, and that the location of critical solder joints change from die edges to package corners with the introduction of adhesives.

Thermal Cycle Reliability and Failure Mechanisms of CCGA and PBGA Assemblies With and Without Corner Staking

Area array packages (AAPs) with 1.27 mm pitch have been the packages of choice for commercial applications; they are now starting to be implemented for use in military and aerospace applications. Thermal cycling characteristics of plastic ball grid array (PBGA) and chip scale package assemblies, because of their wide usage for commercial applications, have been extensively reported on in literature. Thermal cycling represents the on-off environmental condition for most electronic products and therefore is a key factor that defines reliability. However, very limited data is available for thermal cycling behavior of ceramic packages commonly used for the aerospace applications. For high reliability applications, numerous AAPs are available with an identical design pattern both in ceramic and plastic packages. This paper compares assembly reliability of ceramic and plastic packages with the identical inputs/outputs (I/Os) and pattern. The ceramic package was in the form of ceramic column grid array (CCGA) with 560 I/Os peripheral array with the identical pad design as its plastic counterpart. The effects of the following key parameters on reliability of both CCGA and PBGA assemblies were investigated:(1) thermal cycle ranges, -50degC/75degC, -55degC/100degC, and -55degC/125degC; (2) corner staking on failure mechanisms for two thermal cycle profiles, -55degC/125degC and -50degC/75degC; (3) package interchangeability, i.e., using PBGA package on CCGA pad design with a larger pad. Packages were assembled on polyimide boards and their daisy chains were continuously monitored. Optical photomicrographs were taken at various thermal cycle intervals to document damage progress and behavior. Representative samples along with their cross-sectional photomicrographs at higher magnification, taken by scanning electron microscopy and analyzed by energy dispersive X-ray, are also presented. The inspection documents were used to determine crack propagation and failure analyses for packages with and without corner staking. In assemblies with corner staking adhesive, a transition in failure from corner columns to center columns was observed when maximum temperature in thermal cycling profiles changed. This is a new failure mechanism not reported on in literature. Finite element analysis (FEA) was used to predict such global failure mode changes. FEA findings are also presented.

Combining radial basis function neural network and genetic algorithm to improve HDD driver IC chip scale package assembly yield

In recent years, the future trend of micro HDD driver IC for large capacity micro HDD is to become lighter, thinner, shorter and smaller. Among all the options available for micro HDD driver IC's assembly, warpage is an important issue related to micro HDD driver IC manufacturability and reliability. The optimal packaging manufacturing process for driver IC for micro HDD is chip scale package (CSP). However, the production and assemble process for CSP is much more difficult. The aim of this study is to improve the lower warpage properties for 0.65mm CSP assembly yield using a model based on a radial basis function network (RBFN), and the optimal HDD packaging process parameter design is achieved through a genetic algorithm (GA).

Experimental and Numerical Investigation of the Reliability of Double-Sided Area Array Assemblies

One of the primary advantages of surface mount technology (SMT) over through-hole technology is that SMT allows the assembly of components on both sides of the printed circuit board (PCB). Currently, area array components such as ball grid array (BGA) and chip-scale package (CSP) assemblies are being used in double-sided configurations for network and memory device applications as they reduce the routing space and improve electrical performance (Shiah, A. C., and Zhou, X., 2002, “A Low Cost Reliability Assessment for Double-Sided Mirror-Imaged Flip Chip BGA Assemblies,” Proceedings of the Seventh Annual Pan Pacific Microelectronics Symposium, Maui, Hawaii, pp. 7–15, and Xie, D., and Yi, S., 2001, “Reliability Design and Experimental work for Mirror Image CSP Assembly”, Proceedings of the International Symposium on Microelectronics, Baltimore, October, pp. 417–422). These assemblies typically use a “mirror image” configuration wherein the components are placed on either side of the PCB directly over each other; however, other configurations are possible. Double-sided assemblies pose challenges for thermal dissipation, inspection, rework, and thermal cycling reliability. The scope of this paper is the study of the reliability of double-sided assemblies both experimentally and through numerical simulation. The assemblies studied include single-sided, mirror-imaged, 50% offset CSP assemblies, CSPs with capacitors on the backside, single-sided, mirror-imaged plastic ball grid arrays (PBGAs), quad flat pack (QFP)/BGA mixed assemblies. The effect of assembly stiffness on thermal cycling reliability was investigated. To assess the assembly flexural stiffness and its effect on the thermal cycling reliability, a three-point bending measurement was performed. Accelerated thermal cycling cycles to failure were documented for all assemblies and the data were used to calculate the characteristic life. In general, a 2X to 3X decrease in reliability was observed for mirror-image assemblies when compared to single-sided assemblies for both BGAs and CSPs on 62mil test boards. The reliability of mirror-image assemblies when one component was an area array device and the other was a QFP was comparable to the reliability of the single-sided area array assemblies alone, that is, the QFP had almost no influence on the double-sided reliability when used with an area array component. Moiré interferometry was used to study the displacement distribution in the solder joints at specific locations in the packages. Data from the reliability and moiré measurements were correlated with predictions generated from three-dimensional finite element models of the assemblies. The models incorporated nonlinear and time-temperature dependent solder material properties and they were used to estimate the fatigue life of the solder joints and to obtain an estimate of the overall package reliability using Darveaux’s crack propagation method.

Reliability studies and design improvement of mirror image CSP assembly

In this paper, both simulation and testing techniques were used to address the reliability issue of mirror chip scale package (CSP) assembly. First, finite element modeling was employed to study the stress and strain of a mirror image CSP with comparison to a single-sided CSP. The study clearly illustrates that the strain distribution is not equally distributed across both sides of the CSP. The highest strain on one side of the mirror image CSP is often larger than the other one, which reduced the reliability of the package as a whole. In order to study the effects on the reliability of the mirror image CSP assembly, several parameters, such as PCB board materials selection, board thickness and warpage, PCB via design and routing, were investigated. Moreover, a design of experiment matrix was constructed to identify significant factors to minimize the highest strain in solder joints of mirror image. The test vehicle was then designed and assembled. Thermal cycling (0 to 100 °C) and thermal shock tests were thereafter performed to the mirror image CSPs and single-sided CSPs to compare with the simulation results.

Guidelines to select underfills for flip chip on board assemblies and compliant interposers for chip scale package assemblies

The effect of thermomechanical properties of underfill and compliant interposer materials, such as coefficient of thermal expansion (CTE) and stiffness (Young's modulus) on reliability of flip chip on board (FCOB) and chip scale packages (CSPs) under thermal cycling stresses is investigated in this study. Quasi-three-dimensional viscoplastic stress analysis using finite element modeling (FEM) is combined with an energy partitioning (EP) model for creep-fatigue damage accumulation to predict the fatigue durability for a given thermal cycle. Parametric FEM simulations are performed for five different CTEs and five different stiffnesses of the underfill and compliant interposer materials. The creep work dissipation due to thermal cycling is estimated with quasi 3-D model, while 3-D model is used to estimate the hydrostatic stresses. To minimize the computational effort, the 3-D analysis is conducted only for the extreme values of the two parameters (CTE and stiffness) and the results are interpolated for intermediate values. The results show that the stiffness of the underfill material as well as the CTE play important role in influencing the fatigue life of FCOB assemblies. The fatigue durability increases as underfill stiffness and CTE increase. In the case of compliant interposers, the reverse is true and durability increases as interposer stiffness decreases. Furthermore, the interposer CTE affects the fatigue durability more significantly than underfill CTE, with durability increasing as CTE decreases. The eventual goal is to define the optimum design parameters of the FCOB underfill and CSP interposer, in order to maximize the fatigue endurance of the solder joints under cyclic thermal loading environments.

Accelerated Thermal Cycling and Failure Mechanisms for BGA and CSP Assemblies

This paper reviews the accelerated thermal cycling test methods that are currently used by industry to characterize the interconnect reliability of commercial-off-the-shelf (COTS) ball grid array (BGA) and chip scale package (CSP) assemblies. Acceleration induced failure mechanisms varied from conventional surface mount (SM) failures for CSPs. Examples of unrealistic life projections for other CSPs are also presented. The cumulative cycles-to-failure for ceramic BGA assemblies performed under different conditions, including plots of their two Weibull parameters, are presented. The results are for cycles in the range of −30°C to 100°C, −55°C to 100°C, and −55°C to 125°C. Failure mechanisms, as well as cycles to failure for thermal shock and thermal cycling conditions in the range of −55°C to 125°C, were compared. Projection to other temperature cycling ranges using a modified Coffin-Manson relationship is also presented. [S1043-7398(00)00104-3]

CSP compatibility in the SMT assembly process

To achieve integration of chip scale package (CSP) devices into main stream surface mount technology (SMT) assembly, various experiments have been required. In process development, experiences learned from flip chip attach and ball grid array (BGA) assembly were utilized. Key process parameters for CSP assembly were defined and some of those key factors were optimized. They will be presented in this paper. Some observations during prototype build have been documented for correlation with reliability results in the future. The requirements for further CSP assembly studies will also be addressed in this paper.