Chip Real Estate Research Articles

Influence of reaction cell electrodes on organic electrochemical transistors

Organic electrochemical transistors (OECTs) hold great potential in various applications, including biosensing and neural network computation. Traditional “all-in-one” OECT device architecture faces the problems of unclear amplification mechanisms and complex side reactions, to name a few. The reaction cell OECT (RC-OECT) device architecture, proposed by Ting et al. [Adv. Funct. Mater. 31(19), 2010868 (2021)], effectively resolves these problems. Furthermore, in many applications of OECTs, such as high throughput (bio)sensing, an OECT device array instead of a single OECT is needed. Therefore, the size (area) of the OECT device, which represents the amount of occupied chip real estate and the integration of the device, matters. In this paper, we developed a hydrogen peroxide sensor based on the RC-OECT. We utilized an RC cathode modified by the poly(3,4-ethylenedioxythiophene) polystyrene sulfonate film and a Ag/AgCl OECT gate electrode for facilitating device integration, varied RC anode area, and achieved optimization of at least one of the two parameters, sensitivity and lower limit of detection (LLoD), in conjunction with the level of integration of the device. Multiple quantitative sensitivity metrics have been adopted in this work. We also evaluated the correlation between RC anode area and LLoD. In addition, a mechanistic analysis of the RC-OECT device structure, in terms of faradic and non-faradaic currents, was carried out to illustrate the interplay between sensing performance and the electrode area of the reaction cell. This mechanistic analysis provides insights for miniaturizing OECT devices with the RC-OECT architecture.

Scalable High-Precision Trimming of Photonic Resonances by Polymer Exposure to Energetic Beams.

Integrated photonic circuits (PICs) have seen an explosion in interest, through to commercialization in the past decade. Most PICs rely on sharp resonances to modulate, steer, and multiplex signals. However, the spectral characteristics of high-quality resonances are highly sensitive to small variations in fabrication and material constants, which limits their applicability. Active tuning mechanisms are commonly employed to account for such deviations, consuming energy and occupying valuable chip real estate. Readily employable, accurate, and highly scalable mechanisms to tailor the modal properties of photonic integrated circuits are urgently required. Here, we present an elegant and powerful solution to achieve this in a scalable manner during the semiconductor fabrication process using existing lithography tools: by exploiting the volume shrinkage exhibited by certain polymers to permanently modulate the waveguide's effective index. This technique enables broadband and lossless tuning with immediate applicability in wide-ranging applications in optical computing, telecommunications, and free-space optics.

Spin Wave Based Approximate Computing

By their very nature Spin Waves (SWs) enable the realization of energy efficient circuits, as they propagate and interfere within waveguides without consuming noticeable energy. However, SW computing can be even more energy efficient by taking advantage of the approximate computing paradigm as many applications, e.g., multimedia and social media, are error-tolerant. In this paper, we propose an ultra-low energy Approximate Full Adder (AFA) and an Approximate 2-bit inputs Multiplier (AMUL). AFA consists of one Majority gate whereas AMUL is built by means of 3 AND gates. We validate the correct functionality of our proposal by means of micromagnetic simulations and evaluate AFA's figures of merit against state-of-the-art accurate SW, 7nm CMOS, Spin Hall Effect (SHE), Domain Wall Motion (DWM), accurate and approximate 45nm CMOS, Magnetic Tunnel Junction (MTJ), and Spin-CMOS FA implementations. Our results indicate that AFA consumes 38% and 6% less energy than state-of-the-art accurate SW and 7nm CMOS FA implementations, respectively. Moreover, it saves 56% and 20% energy when compared with accurate and approximate 45nm CMOS counterparts, respectively. Furthermore, it provides 2 orders of magnitude energy reduction when compared with accurate SHE, accurate and approximate DWM, MTJ, and Spin-CMOS, counterparts. In addition, it achieves the same error rate as approximate 45nm CMOS and Spin-CMOS FAs whereas it exhibits 50% less error rate than the approximate DWM FA. Last but not least, it outperforms its contenders in terms of area by saving at least 29% chip real-estate. AMUL is evaluated and compared with state-of-the-art SW and 16nm CMOS accurate and approximate designs. The evaluation results indicate that AMUL energy consumption is at least 2.8x and 2.6x smaller than the one of state-of-the-art SW and 16nm CMOS accurate and approximate designs, respectively. AMUL has an error rate of 25%, whereas the approximate CMOS multiplier has an error rate of 38%, and requires at least 64% less chip real-estate than the CMOS counterpart.

Non-Binary Spin Wave Based Circuit Design

By their very nature, Spin Waves (SWs) excited at the same frequency but different amplitudes, propagate through waveguides and interfere with each other at the expense of ultra-low energy consumption. In addition, all (part) of the SW energy can be moved from one waveguide to another by means of coupling effects. In this paper we make use of these SW features and introduce a novel non Boolean algebra based paradigm, which enables domain conversion free ultra-low energy consumption SW based computing. Subsequently, we leverage this computing paradigm by designing a non-binary spin wave adder, which we validate by means of micro-magnetic simulation. To get more inside on the proposed adder potential we assume a 2-bit adder implementation as discussion vehicle, evaluate its area, delay, and energy consumption, and compare it with conventional SW and 7 nm CMOS counterparts. The results indicate that our proposal diminishes the energy consumption by a factor of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3.14 \times $ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$6 \times $ </tex-math></inline-formula> , when compared with the conventional SW and 7 nm CMOS functionally equivalent designs, respectively. Furthermore, the proposed non-binary adder implementation requires the least number of devices, which indicates its potential for small chip real-estate realizations.

An Integrated Compact Phase Shifter With a Single Analog Control

This letter presents a new circuit topology for a vector sum phase shifter where the amplitudes and phases of I and Q are simultaneously varied using a single analog control signal. The simultaneous adjustment of amplitudes and phases of I and Q allows for the vector sum's large phase tuning while maintaining its amplitude. Moreover, various functions of vector summation are all performed in a single stage, minimizing the chip real estate and power consumption. The maximum range of analog phase tuning with a constant amplitude is theoretically 180°, but in practice, it is limited by the tuning range of the utilized varactors. To achieve a large phase tuning range given varactors with limited tunability, digital control has been added to allow for coarse tuning of the phase. The utilized approach for coarse phase tuning preserves the chip area and power consumption but causes amplitude variation. The phase shifter performance is verified by simulations and measurements.

A Spin Wave-Based Approximate 4:2 Compressor: Seeking the most energy-efficient digital computing paradigm

In this article, we propose an energy-efficient spin wave (SW)-based approximate 4:2 compressor including three- and five-input majority gates. We validate our proposal by means of micromagnetic simulations and assess and compare its performance with state-of-the-art SW 45-nm CMOS and spin-CMOS counterparts. The evaluation results indicate that the proposed compressor consumes 31.5% less energy than its accurate SW-design version. Furthermore, it has the same energy consumption and error rate as a directional coupler (DC)-based approximate compressor, but it exhibits a 3× shorter delay. In addition, it consumes 14% less energy while having a 17% lower average error rate than its approximate 45-nm CMOS counterpart. When compared with other emerging technologies, the proposed compressor outperforms the approximate spin-CMOS-based compressor by three orders of magnitude in terms of energy consumption while providing the same error rate. Finally, the proposed compressor requires the smallest chip real estate measured in terms of devices.

Deep Learning Enabled Design of Complex Transmission Matrices for Universal Optical Components

Recent breakthroughs in photonics-based quantum, neuromorphic and analogue processing have pointed out the need for new schemes for fully programmable nanophotonic devices. Universal optical elements based on interferometer meshes are underpinning many of these new technologies, however this is achieved at the cost of an overall footprint that is very large compared to the limited chip real estate, restricting the scalability of this approach. Here, we consider an ultracompact platform for low-loss programmable elements using the complex transmission matrix of a multi-port multimode waveguide. We propose a deep learning inverse network approach to design arbitrary transmission matrices using patterns of weakly scattering perturbations. The demonstrated technique allows control over both the intensity and phase in a multiport device at a four orders reduced device footprint compared to conventional technologies, thus opening the door for large-scale integrated universal networks.

Femtojoule per MAC Neuromorphic Photonics: An Energy and Technology Roadmap

Photonic artificial neural networks have garnered enormous attention due to their potential to perform multiply-accumulate (MAC) operations at much higher clock rates and consuming significantly lower power and chip real-estate compared to digital electronic alternatives. Herein, we present a comprehensive power consumption analysis of photonic neurons, taking into account global design parameters and concluding to analytical expressions for the neuron's energy- and footprint efficiencies. We identify the optimal design-space and analyze the performance plateaus and their dependence on a range of physical parameters, highlighting the existence of an optimal data-rate for maximizing the energy efficiency. Following a survey of the best-in-class integrated photonic devices, including on-chip lasers, photodetectors, modulators and weighting elements, the mathematically calculated energy and footprint efficiencies are mapped into real photonic neuron deployment scenarios. We reveal that silicon photonics can compete with the best-performing currently available digital electronic neural network engines, reaching TMAC/s/mm2 footprint- and sub-pJ/MAC energy efficiencies. Simultaneously, neuromorphic plasmonics, plasmo-photonics and sub-wavelength photonics hold the credentials for 1 to 3 orders of magnitude improvements even when the laser requirements and a reasonable waveguide pitch are accounted for, promising performance at a few fJ/MAC and up to a few TMAC/s/mm2.

Integrated On-Chip Transformers: Recent Progress in the Design, Layout, Modeling and Fabrication.

On-chip transformers are considered to be the primary components in many RF wireless applications. This paper provides an in-depth review of on-chip transformers, starting with a presentation on the various equivalent circuit models to represent transformer behavior and characterize their performance. Next, a comparative study on the different design and layout strategies is provided, and the fabrication techniques for on-chip implementation of transformers are discussed. The critical performance parameters to characterize on-chip transformers, such as the Q-factor, coupling factor (k), resonance frequency (fSR), and others, are discussed with reference to trade-offs in silicon chip real-estate. The performance parameters and area requirements for different types of on-chip transformers are summarized in tabular form and compared. Several techniques for performance enhancement of on-chip transformers, including the different types of micromachining and integration approaches stemming from MEMS (microelectromechanical systems) technologies are also analyzed. Lastly, the different uses and applications of on-chip transformers are discussed to highlight the evolution of on-chip transformer technology over the recent years and provide directions for future work in this field.

Continuum Computing - on a New Performance Trajectory beyond Exascale

The end of Moore's Law is a cliche that none the less is a hard barrier to future scaling of high performance computing systems. A factor of about 4x in device density is all that is left of this form of improved throughput with a 5x gain required just to get to the milestone of exascale. The remaining sources of performance improvement are better delivered efficiency of more than 10x and alternative architectures to make better use of chip real estate. This paper will discuss the set of principles guiding a potential future of non-von Neumann architectures as adopted by the experimental class of Continuum Computer Architecture (CCA). It is being explored by the Semantic Memory Architecture Research Team (SMART) at Indiana University. CCA comprises a homogeneous aggregation of cellular components (function cells) which are orders of magnitude smaller than lightweight cores and individually is unable to accomplish a computation but in combination can do so with extreme cost efficiency and unprecedented scalability. It will be seen that a path exists based on such unconventional methods like neuromorphic computing or dataflow that not only will meet the likely exascale milestone in the same time with much better power, cost, and size but also will set a new performance trajectory leading to Zetaflops capability before 2030.

MBus: A Fully Synthesizable Low-power Portable Interconnect Bus for Millimeter-scale Sensor Systems

This paper presents a fully synthesizable low power interconnect bus for millimeter-scale wireless sensor nodes. A segmented ring bus topology minimizes the required chip real estate with low input/output pad count for ultra-small form factors. By avoiding the conventional open drain-based solution, the bus can be fully synthesizable. Low power is achieved by obviating a need for local oscillators in member nodes. Also, aggressive power gating allows low-power standby mode with only 53 gates powered on. An integrated wakeup scheme is compatible with a power management unit that has nW standby mode. A 3-module system including the bus is fabricated in a 180 nm process. The entire system consumes 8 nW in standby mode, and the bus achieves 17.5 pJ/bit/chip.

Leak-tight vertical membrane microvalves.

Pneumatic microvalves are fundamental control components in a large range of microfluidic applications. Their key performance parameters are small size, i.e. occupying a minimum of microfluidic real estate, low flow resistance in the open state, and leak-tight closing at limited control pressures. In this work we present the successful design, realization and evaluation of the first leak-tight, vertical membrane, pneumatic microvalves. The realization of the vertical membrane microvalves is enabled by a novel dual-sided molding method for microstructuring monolithic 3D microfluidic networks in PDMS in a single step, eliminating the need for layer-to-layer alignment during bonding. We demonstrate minimum lateral device features down to 20-30 μm in size, and vertical via density of ∼30 000 per cm(2), which provides significant gains in chip real estate compared to previously reported PDMS manufacturing methods. In contrast to horizontal membrane microvalves, there are no manufacturing restrictions on the cross-sectional geometry of the flow channel of the vertical membrane microvalves. This allows tuning the design towards lower closing pressure or lower open state flow resistance compared to those of horizontal membrane microvalves.

Heterogeneous Multi-core Architectures

Transistor count continues to increase for silicon devices following Moore's Law. But the failure of Dennard scaling has brought the computing community to a crossroad where power has become the major limiting factor. Thus future chips can have many cores; but only a fraction of them can be switched on at any point in time. This dark silicon era, where significant fraction of the chip real estate remains dark, has necessitated a fundamental rethinking in architectural designs. In this context, heterogeneous multi-core architectures combining functionality and performance-wise divergent mix of processing cores (CPU, GPU, special-purpose accelerators, and reconfigurable computing) offer a promising option. Heterogeneous multi-cores can potentially provide energy-efficient computation as only the cores most suitable for the current computation need to be switched on. This article presents an overview of the state-of-the-art in heterogeneous multi-core landscape.

A Real-Time Motion-Feature-Extraction VLSI Employing Digital-Pixel-Sensor-Based Parallel Architecture

A very-large-scale integration capable of extracting motion features from moving images in real time has been developed employing row-parallel and pixel-parallel architectures based on the digital pixel sensor technology. Directional edge filtering of input images is carried out in row-parallel processing to minimize the chip real estate. To achieve a real-time response of the system, a fully pixel-parallel architecture has been explored in adaptive binarization of filtered images for essential feature extraction as well as in their temporal integration and derivative operations. As a result, self-speed-adaptive motion feature extraction has been established. The chip was designed and fabricated in a 65-nm CMOS technology and used to build an object detection system. Motion-sensitive target image localization was demonstrated as an illustrative example.

Microfluidic serial dilution ladder

Serial dilution is a fundamental procedure that is common to a large number of laboratory protocols. Automation of serial dilution is thus a valuable component for lab-on-a-chip systems. While a handful of different microfluidic strategies for serial dilution have been reported, approaches based on continuous flow mixing inherently consume larger amounts of sample volume and chip real estate. We employ valve-driven circulatory mixing to address these issues and also introduce a novel device structure to store each stage of the dilution process. The dilution strategy is based on sequentially mixing the rungs of a ladder structure. We demonstrate a 7-stage series of 1 : 1 dilutions with R(2) equal to 0.995 in an active device area of 1 cm(2).

Design Considerations and Ring-down Characteristics of Micromachined, High Current Density Capacitors

The need for integrated passive components which meet the stringent power system requirements imposed by increased data rates, signal path density and challenging power distribution network topologies in integrated systems yield diverse motivations for high density, miniaturized capacitors capable of quickly sourcing large quantities of current. These diverse motivations have led to the realization of high density capacitor structures through the means of several technologies. These structures have been evaluated as high-speed, energy storage devices and their respective fabrication technologies have been closely compared for matching integrated circuit speed and density increase, chip current requirements, low resistance, low leakage current, high capacitance and compatibility with relatively high frequencies of operation (~1GHz). These technologies include devices that utilize pn junctions, Schottky barriers, optimized surface area techniques and the utilization of high dielectric constant (high-K) materials, such as hafnium oxide, as a dielectric layer through the means of atomic layer deposition (ALD). The resulting devices were micro-machined, large surface area, thin, high-density capacitor technologies optimized as embedded passive devices for thin silicon interposers. This work outlines the design, fabrication, simulation and testing of each device revision using standard silicon microfabrication processes and silicon interposer technologies. Consequently, capacitive storage devices were micro-machined with geometries which maximize surface area and exhibit the capability of sourcing 100A of current with a response time greater than 100 A/nsec through the use of thin layered, ALD high-K materials. The simulation and testing of these devices show general agreement when subjected to a standard ring-down procedure. This paper provides descriptions and design challenges encountered during fabrication, testing and integration of these passive devices. In addition, potential device integration and implementation strategies for use in silicon interposers are also provided. The modification and revision of several device generations is documented showing increased device capacitance density, maximized current capabilities and minimized effects of series inductance and resistance. The resulting structures are thin, capacitive devices that may be micro-machined using industry standard Si MEMS processes and are compatible with Si interposer 3D technologies. The subsequent design processes allow integrated passive components to be attached beneath chips in order to maximize system area and minimize the chip real estate required for capacitive energy storage devices.

Fully Parallel Self-Learning Analog Support Vector Machine Employing Compact Gaussian Generation Circuits

An analog support vector machine (SVM) processor employing a fully parallel self-learning circuitry was developed for the classification of highly dimensional patterns. To implement a highly dimensional Gaussian function, which is the most powerful kernel function in classification algorithms but computationally expensive, a compact analog Gaussian generation circuit was developed. By employing this proposed Gaussian generation circuit, a fully parallel self-learning processor based on an SVM algorithm was built for 64 dimension pattern classification. The chip real estate occupied by the processor is very small. The object images from two classes were converted into 64 dimension vectors using the algorithm developed in a previous work and fed into the processor. The learning process autonomously proceeded without any clock-based control and self-converged within a single clock cycle of the system (at 10 MHz). Some test object images were used to verify the learning performance. According to the circuit simulation results, it was shown that all the test images were classified into correct classes in real time. A proof-of-concept chip was designed in a 0.18 µm complementary metal–oxide–semiconductor (CMOS) technology, and the performance of the proposed SVM processor was confirmed from the measurement results of the fabricated chips.

A Path Toward Non-Destructive 3D Metrology for Through-Silicon Vias

As integrated circuit designs are pushed to tighter dimensions, chip real-estate is becoming of increasing value. Much like the growth of a developing city, a common modern approach is to grow the circuits upwards, building one layer on top of another. In this 3D stacking approach, the common issue lies in how to connect the multiple layers, for which direct connections through the silicon substrates have been found to produce the smallest footprint. These through-silicon vias (TSVs) are currently the subject of heavy research and development (R&amp;D) investigation and their efficiencies are, in part, directly related to the occurrence or absence of voids within the metal structures. 3D x-ray microscopy (XRM) has recently been pushed to unprecedented resolution levels and may fit the inspection needs of the TSV R&amp;D community. Using a unique projection-based micro-CT imaging geometry, entire packages may be inspected with as high as 1 μm resolution. This technique delivers non-destructive metrology of the metal fills as well as the post-etch regions in 3D, without the need for physical cutting or sectioning. By employing x-ray optics, resolution as high as 50 nm is now routinely achievable, allowing the detection of far sub-micron voids within the post-metallization TSV structures. These results may be further analyzed for void sizes and void volume fractions per via. Post-etch samples are also well-visualized using this technique, which allows high-resolution inspection of the side walls as well as measurement of the critical dimensions using the same system as for the post-metallization structures.

Obtaining FPGA soft error rate in high performance information systems

Soft errors due to cosmic particles are a growing reliability threat for VLSI systems. The vulnerability of FPGA-based designs to soft errors is higher than ASIC implementations since the majority of chip real estate is dedicated to memory bits, configuration bits, and user bits. Moreover, Single Event Upsets (SEUs) in the configuration bits of SRAM-based FPGAs result in permanent errors in the mapped design. FPGAs are widely used in the implementation of high performance information systems. Since the reliability requirements of these high performance information sub-systems are very stringent, the reliability of the FPGA chips used in the design of such systems plays a critical role in the overall system reliability. In this paper, we compare and validate the soft error rate of FPGA-based designs used in the Logical Unit Module board of a commercial information system with the field error rates obtained from actual field failure data. This comparison confirms that our analytical tool is very accurate (there is an 81% overlap in FIT rate range obtained with our analytical modeling framework and the field failure data studied). It can be used for identifying vulnerable modules within the FPGA for cost-effective reliability improvement.

Soft Error Susceptibility Analysis of SRAM-Based FPGAs in High-Performance Information Systems

Soft errors due to cosmic particles are a growing reliability threat for VLSI systems. The vulnerability of FPGA-based designs to soft errors is higher than ASIC implementations since the majority of chip real estate is dedicated to memory bits, configuration bits, and user bits. Moreover, single event upsets (SEUs) in the configuration bits of SRAM-based FPGAs result in permanent errors in the mapped design. In this paper we analyze the soft error vulnerability of FPGAs used in information systems. Since the reliability requirements of these high performance information subsystems are very stringent, the reliability of the FPGA chips used in the design of such systems plays a critical role in overall system reliability. We present an analytical approach (versus fault injection) for soft error rate estimation in FPGA-based designs. We also validate the projections produced by our analytical model using field error rates obtained from failure data obtained from a large FPGA-based design used in the logical unit module board of a commercial information system. This comparison confirms that the projections obtained from our analytical tool are accurate (there is an 81% overlap in FIT rate range obtained with our analytical modeling framework and the field failure data studied).