Chip Power Distribution Network Research Articles

Active Integrated Devices PDN Balanced Truncation Reduction Method

For EMC simulation, the vector fitting model is transformed into time domain state equation model. Then the system is balanced. Then the reduced model can be obtained by removing the states corresponding to the small HSV (Hankel Singular Values). The order of the reduced model is determined by the singular curvature spectrum. Finally, balanced truncation model reduction method is used on a sample chip PDN (Power Distribution Network) and compared with the performance of the AWE (Asymptotic Waveform Evaluation) method. Simulation results show that the proposed method can operate in a wide frequency range and has smaller error and faster speed.

GHz EMI Characteristics of 3D Stacked Chip PDN with Through Silicon Via (TSV) Connections

GHz electromagnetic interference (EMI) characteristics are analyzed for a 3dimensional (3D) stacked chip power distribution network (PDN) with through silicon via (TSV) connections. The EMI problem is mostly raised by P/G (power/ground) noise due to high switching current magnitudes and high PDN impedances. The 3D stacked chip PDN is decomposed into P/G TSVs and vertically stacked capacitive chip PDNs. The TSV inductances combine with the chip PDN capacitances produce resonances and increase the PDN impedance level in the GHz frequency range. These effects depend on stacking configurations and P/G TSV designs and are analyzed using the P/G TSV model and chip PDN model. When a small size chip PDN and a large size chip PDN are stacked, the small one's impedance is more seriously affected by TSV effects and shows higher levels. As a P/G TSV location is moved to a corner of the chip PDNs, larger PDN impedances appear. When P/G TSV numbers are enlarged, the TSV effects push the resonances to a higher frequency range. As a small size chip PDN is located closer to the center of a large size chip PDN, the TSV effects are enhanced.