Chip Pin Research Articles

TCI Tester: A Chip Tester for Inductive Coupling Wireless Through-Chip Interface

The building block computation system is constructed by stacking various chips three-dimensionally. The stacked chips incorporate the same TCI IP (Through Chip Interface Intellectual Property) but cannot provide identical characteristics, requiring adjustments in power supply and bias voltage. However, providing characteristics measurement hardware for all chips is difficult due to the limitation of chip area or pin numbers. To address this problem, we developed TCI Tester, a small chip to measure electric characteristics by stacking on TCI of every chip. By stacking two TCI Tester chips, it appears that the up-directional data transfer has a stricter condition than down directional one on power supply voltage and operational frequency. Also, the transfer performance is poorer than designed. Similar measurement results are obtained by stacking TCI Tester on other chips with TCI IP. To investigate the reason, we analyzed the power grid resistance of various chips with the TCI IP. Results also showed that the chips with higher resistance have a narrow operational condition and poorer performance. The results suggest that the power grid design is important for keeping the performance through the TCI channel.

The study of failure characteristics of MCU based on the after-sale reverse analysis

In recent years, smart door locks including password keyboards, fingerprint recognition and communication function have seen explosive growth, and a large number of enterprises engaged in the manufacture of intelligent home appliances. As a result, there are many after-sales problems, especially the product without power, no reaction phenomenon caused by the failure of the master control chip is relatively common, which greatly affects the user experience. For this, this paper takes mainstream smart door lock products on the market as the research object, and a series of failure analyses and root cause searches are executed to find the reasons for master control chip failure. The research shows that the failure of the intelligent door lock master chip is caused by the static damage of the chip pin due to insufficient static protection, which is directly related to the improper production and assembly process.

Automatic Detection of Chip Pin Defect in Semiconductor Assembly Using Vision Measurement

Abstract With the development of semiconductor assembly technology, the continuous requirement for the improvement of chip quality caused an increasing pressure on the assembly manufacturing process. The defects of chip pin had been mostly verified by manual inspection, which has low efficiency, high cost, and low reliability. In this paper, we propose a vision measurement method to detect the chip pin defects, such as the pin warping and collapse that heavily influence the quality of chip assembly. This task is performed by extracting the corner feature of the chip pins, computing the corresponding point pairs in the binocular sequence images, and reconstructing the target features of the chip. In the corner feature step, the corner detection of the pins using the gradient correlation matrices (GCM), and the feature point extraction of the chip package body surface using the crossing points of the fitting lines are introduced, respectively. After obtaining the corresponding point pairs, the feature points are utilized to reconstruct the three dimensional (3D) coordinate information in the binocular vision measurement system, and the key geometry dimension of the pins is computed, which reflects whether the quality of the chip pins is up to the standard. The proposed method is evaluated on the chip data, and the effectiveness is also verified by the comparison experiments.

Research on RF Voltage Measurement Method of Chip Pins

As the core device of electronic equipment, integrated circuit (IC) usually produces large high-frequency electromagnetic interference. In order to study the generation mechanism and suppression methods of such noise, accurate noise measurement and extraction must be carried out. At present, the measurement standard of chip level electromagnetic compatibility is not perfect, and the high-frequency characteristics of pin noise are difficult to be measured accurately. In order to achieve accurate chip pin RF voltage measurement, this paper designs a chip pin RF voltage measurement method, establishes the 3D model of the chip pin RF voltage measurement module, studies the effects of its wiring, via, substrate dielectric constant and other parameters on its high-frequency signal transmission performance, and then optimizes the module. Simulation and experimental results show that the optimization method effectively improves its high-frequency signal transmission characteristics. Finally, the RF voltage of the output pin of the active crystal oscillator is extracted by using the detection system designed in this paper.

Electronically Switchable Broadband Metamaterial Absorber

In this study, the novel electronically switchable broadband metamaterial absorber, using a PIN diode, is proposed. The unit cell of the absorber was designed with a Jerusalem-cross resonator and an additive ring structure, based on the FR-4 dielectric substrate. Chip resistors and PIN diodes were used to provide both a broadband characteristic and a switching capability. To satisfy the polarization insensitivity, the unit cell was designed as a symmetrical structure, including the DC bias network, electronic devices, and conductor patterns. The performance of the proposed absorber was verified using full-wave simulation and measurements. When the PIN diode was in the ON state, the proposed absorber had a 90% absorption bandwidth from 8.45–9.3 GHz. Moreover, when the PIN diode was in the OFF state, the 90% absorption bandwidth was 9.2–10.45 GHz. Therefore, the absorption band was successfully switched between the low-frequency band and the high-frequency band as the PIN diode was switched between the ON and OFF states. Furthermore, the unit cell of the proposed absorber was designed as a symmetrical structure, and its performance showed insensitivity with respect to the polarization angle.

Alleviate Chip Pin Constraint for Multicore Processor by On/Off-Chip Power Delivery System Codesign

The number of chip pins is limited due to the cost and reliability issues of sophisticated packages, and it is predicted that the chip pin count will be overstretched to satisfy the requirements of both power delivery and memory access. The gap between the achievable pin count and the demand will increase as the technology scales, due to the increasing computation resources and supply current. Pin reduction techniques are thus required for continued computing performance growth. In this article, we propose a chip pin constraint alleviation strategy, through on/off-chip power delivery system co-design, to effectively reduce the demand for power pins. An analytical model of a power delivery system, consisting of on/off-chip regulators and a power delivery network, is proposed to evaluate the influence of regulator design and package conduction loss. By combining this model with a multi-core processor model of performance and memory bandwidth requirements, we characterize the entire multi-core processor system to investigate the relationship between the chip pin constraint and performance in multi-core processor scaling and the effectiveness of our strategy. Experiments show that with the conventional power delivery system design, the chip pin constraint severely limits the performance growth as the technology scales. Using the on/off-chip power delivery system co-design, our strategy achieves a significant pin count reduction, for example, 31.3% at the 8nm technology node, compared to the conventional design with the same chip performance, while, provided with the same chip pin count, it is able to improve, by 35.0%, the chip performance at 8nm compared to the conventional design. For real applications of different parallelism, our strategy outperforms its counterpart, with a 23.7% performance improvement on average at the 8nm technology node.

Improve Chip Pin Performance Using Optical Interconnects

With the fast development of processor chips, power-efficient, high-bandwidth, and low-latency interchip interconnects become more and more important. Studies show that the bandwidth of traditional parallel interconnects with low I/O clock frequencies will become bottlenecks in the near future. To solve this problem, two types of high-bandwidth interchip interconnects are developed. Low-swing differential electrical interconnects have widely been used in high-speed I/O designs. On the other hand, optical interconnects promise high bandwidth, low latency, and could improve the chip pin performance for manycore processors. They are becoming potential alternatives for electrical interconnects. This paper systematically models these two types of interconnects in terms of crosstalk noises, attenuation, and receiver sensitivities. Based on the proposed models, we developed optical and electrical interfaces and links (OEIL) and an analysis tool for OEIL. The OEIL can be used to analyze the energy consumption, bandwidth density, and latency of interconnects. Analytical models are verified by the results of published experiments. It shows that the optical interconnects have much higher bandwidth densities than the electrical interconnects. With this feature, the optical interconnects can significantly reduce I/O pin count compared with the electrical interconnects. For example, they can save at least 92% signal pins when connecting chips more than 25 cm (10 in) apart. The energy consumption of optical interconnects is comparable with that of electrical interconnects, and the latency of polymer waveguide-based optical interconnects is 18% less than that of electrical interconnect.

Application of Improved Canny Algorithm on the IC Chip pin Inspection

Machine vision is widely used in chip pin automation detection of defects, the accuracy of image edge extraction for detection result has very big effect. Canny edge detection algorithm is a kind of edge detection algorithm which have good comprehensive evaluation, but the Gaussian filter algorithm it used may cause image too smooth and fuzzy of the edge, and it is very sensitive for impulse noise. This paper discusses the improved methods of Canny, proposes an improved switch median filter algorithm, which is applied into Canny algorithm, makes the edge of IC Chip pin more complete and remove noise better.

Jitter models for the design and test of Gbps-speed serial interconnects

We present a comprehensive analysis of jitter causes and types, and develops accurate jitter models for design and test of high-speed interconnects. The recent deployment of gigabit-per-second (Gbps) serial I/O interconnects aims at overcoming data transfer bottlenecks resulting from the limited ability to increase chip pin counts in parallel bus architectures. The traditional measure of a communication link's performance has been its associated bit error rate (BER), which is the ratio of the number of bits received in error to the total number of bits transmitted. When data rates increase, jitter magnitude and signal amplitude noise must decrease to maintain the same BER. As data rates exceed 1 Gbps, a slight increase in jitter or amplitude noise has a far greater effect on the BER.

High performance package designs for a 1 GHz microprocessor

This paper describes the architecture and design of an organic land grid array (OLGA) and a flip chip pin grid array (FCPGA) package for a 32 b microprocessor with a clock frequency of 1 GHz and an I/O bus designed to run at 133 MHz. Cost and performance targets and compatibility with existing systems are the key accomplishments of this design project. Issues and implementation details of each of these aspects are discussed and contrasted here. This paper concentrates on the processor performance issues associated with the package routing and power delivery. To overcome high inductance associated with the socket and package pins in the FCPGA package, decoupling capacitors were placed on the underside of the package substrate. This paper discusses an optimal placement scheme for the capacitors and their effectiveness in performance improvement of the system compared to the OLGA package case.

Method for the deviation inspection of integrated circuit chip pin based on Harr wavelet transform

Nankai UniversityInstitute of Modern OpticsOpto-electronic Information Science andTechnology Laboratory, MOETianjin, 300071, ChinaE-mail: gangluo@sun.nankai.edu.cnAbstract. A fast method for chip pin location inspection based on theHarr wavelet transform is presented. A cross line at the pin tip is ana-lyzed, and the method locates the central line of a pin according to thezero crossing position of the transform of the 1-D cross line without the-oretical error. The requirement of being theoretically error free is that theconstant segment of the pin image is wider than 2 pixels. The experimentshows a measurement precision of 1/40 pixel.

Design and performance evaluation of microprocessor packaging capacitors using integrated capacitor-via-plane model

As clock speeds increase into the gigahertz regime and rise times decrease into the picosecond regime, the interaction between capacitors and power/ground planes of a package, interposer, or board on which they are mounted becomes vitally important to the performance of a power delivery system. To include the interaction, this paper provides an integrated model for a discrete capacitor mounted on pads over vias connected to power/ground planes with degassing holes. The mutual inductance between capacitor pads, vias, and power/ground planes are completely modeled. Through optimized via and capacitor pads placement designs, our modeling results show that the mutual inductance drastically changes the total loop inductance as compared to the self-inductance of the capacitor. To validate the integrated modeling method, a test package is built. A measurement technique is introduced to evaluate the total loop inductance of the test package with various capacitor form factors and types. The predicted results match well with the measured data. This paper discusses further the usage of the three-dimensional (3-D) integrated model for actual implementation of decoupling capacitors on packages in order to ensure the effectiveness of the capacitors. The first decoupling capacitor placement design on package that we will discuss is the Plastic Pin Grid Array (PPGA) package for Intel's CPU. Through the three-dimensional (3-D) integrated modeling, the inductance value of the power delivery system with and without capacitors are extracted. It was found that due to the pin-out constraint of CPU PPGA products, as well as unfavorable PPGA package design rules, decoupling capacitors placed in PPGA packages are not effective due to high loop inductance. The second package that we will discuss is the Flip Chip Pin Grid Array (FC-PGA) package, which is for Intel's future CPU packaging. It is found that the decoupling capacitor placement on the FC-PGA highly improves the performance of the power delivery system. For the same amount of cost, the total loop inductance for FCPGA package decoupling capacitors is found to be 1/9th the total loop inductance for the PPGA package.

A methodology and design tools to support system-level VLSI design

System-level design involves making major design decisions without having accurate information on the eventual system characteristics. This paper presents a novel constraint-driven methodology to support system-level design. The software assists a designer or a tool in partitioning behavioral specifications onto multiple VLSI chips and in system design while satisfying hard constraints such as individual chip areas, chip pin counts, system throughput (inverse of system initiation interval) and system latency (delay). The software uses search and estimation techniques to perform comprehensive design-space exploration and evaluates partitions supplied by the user or by other synthesis software. The technique determines what design characteristics each partition must possess in order to satisfy area, pin, throughput and latency constraints. The paper also includes results of extensive experiments with the methodology. >

Communication Structures for Large Networks of Microcomputers

This paper compares nine interconnection schemes and introduces dual-bus hypercubes, a cost-effective method of connecting thousands of dual-port single-chip microcomputers into a room-sized information processing system, a network computer. Each node is a chip containing memory and a pair of processors for tasks and input/output. Nodes are linked by shared communication buses, each conceptually spanning a D-dimensional, W-wide hypercube of N = WD nodes. Each node shares two buses. Each bus is shared by up to W nodes. The number of bus connections per node is fixed to satisfy chip pin limitations.