Chip Package Interaction Reliability Research Articles

Effect of Wiring Density and Pillar Structure on Chip Packaging Interaction for Mixed-Signal Cu Low k Chips

Multilevel finite element analysis (FEA) was used to study the effects of wiring density and solder pillar structure on chip-package interaction (CPI) for advanced Cu/low k mixed-signal chips. The mixed signal chip has analog and digital wiring designs with different metal densities, incorporating extreme low-k (ELK), low-k (LK) and oxide dielectrics in 10 wiring layers. The results are compared with uniform signal chips with uniform metal density on each wiring layer. The first principal stress was found to increase by 1.5 to 3x in the mixed signal chip between the analog and the isolation channel of the ELK and LK layers due to the different wiring density. In addition, the energy release rate (ERR) was significantly increased to reach a critical ERR ratio higher than 1 to drive interfacial delamination, raising serious chip-package interaction (CPI) reliability concern for the mixed signal chip. The results were attributed to the Dundurs effect due to the material mismatch and the nonuniform metal density in the mixed signal chip. In the study of the pillar structure effect, intermetallic compound (IMC) growth was found to be important and can substantially increase the critical ERR ratio to degrade the CPI reliability of the mixed signal chip.

Effect of Different PBO-Based RDL Structures on Chip-Package Interaction Reliability of Wafer Level Package

In this paper, CPI (chip-package interaction) reliability of WLP (wafer level package) was investigated. PBO (Polybenzoxazole)-based RDL (redistribution layer) structure was the primary focus. Firstly, the stress distribution for PBO structures was studied by simulation. Secondly, two types of the chip with different PBO structures completed the accelerating experiments. Based on our investigation, the results of CPI reliability tests are coincident with the simulation data. It can be applied to the early prediction for the risk level of CPI reliability. Additionally, failure mechanisms were figured out for different PBO structures. Design A has the potential risk to suffer corrosion damage owing to exposed SR (seal ring) and CAS (crack stop). Design B has a four times failure rate in THT (Temperature and Humidity Test), which related to hotspots around SR. These results suggest that protecting SR and relieving hotspots effect will effectively enhance CPI reliability performance of WLP.

Bumping Process Impact on the Chip Package Interaction (CPI) Reliability

Abstract Flip chip technology is widely used in advanced integrated circuit (IC) package. Chip package interaction (CPI) became critical in flip chip technology that needed to be addressed to avoid electrical or mechanical failure in products. When addressing CPI challenges, different areas have to be considered, ranging from silicon BEOL design and processing, bumping design and process, package assembly process, assembly bill of material (BOM), and substrate technology. Controlled collapse chip connection (C4) bump technology provided the inter-connection between the IC to package substrate for high-performance, leading-edge microprocessors. It is very critical for chip package interaction (CPI). With the transfer to lead free technology, bumping process plays more and more important role for chip package interaction reliability. In this paper, we focused on bumping process effect on the CPI reliability. The bumping process has been reviewed and CPI reliability issues induced by the bumping process like particles, Ti seed layer deposition, UBM undercut, Cu pad oxidation and contamination, photoresist opening damage have been discussed. Bumping process optimization and corrective actions have been taken to reduce those defects and improve CPI reliability.

CPI Parametric Investigation of UBM-Al Interface for Cu Pillar Flip-Chip Application

Under bump metallization (UBM)–Al delamination is a high-value chip-package interaction reliability problem in flip-chip Cu pillar packaging. We devised a test vehicle for quick reliability assessment. We demonstrate that preclean is a critical step to ensure reliable UBM-Al adhesion and achieve bump shear strength >12 g/mil2 for 15- $\mu \text{m}$ polymer opening. Key parameters affecting bump shear strength, such as UBM critical dimension (CD), polyimide (PI) CD, SiN CD, and PI thickness, were reviewed from both simulation and experimental standpoints and good agreement was achieved between the two. Based on the observed failure mode, a 1-D model was also proposed to correctly predict the experimental trend. Optimum design rules for Cu pillar were outlined. Chip-substrate assembly was demonstrated on 80- $\mu \text{m}$ bump pitch with staggered bump configuration using mass reflow. Progressive thermal cycling was performed to evaluate package performance. Failure mode was found to be solder crack, verifying the improvement in UBM-Al adhesion.

Chip–Package Interaction and Reliability Improvement by Structure Optimization for Ultralow-$k$ Interconnects in Flip-Chip Packages

Mechanical failures in low- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> interlayer dielectrics and related interfaces during flip-chip-packaging processes have raised serious reliability concerns. The problem can be traced to interfacial fracture induced by chip-package interaction (CPI). During the packaging processes, thermal stresses arise from the mismatch in coefficient of thermal expansion between the chip and the substrate, which can be directly coupled into the Cu/low-k interconnect structure to drive interfacial delamination. In this paper, finite-element method is used to evaluate the crack driving force induced by CPI and to examine its impact on the reliability of Cu/low- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> interconnects for 45-nm technology and beyond. First, the characteristics of CPI are investigated for flip-chip packages using a 3-D multilevel global-to-local modeling method where the crack driving force for the interfacial delamination in Cu/low- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> interconnect structures is evaluated. The effects of dielectric and packaging materials are examined for different low- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> dielectrics and Pb-based and Pb-free solders. This study is then extended to explore the potential of using structural optimizations to improve the CPI reliability as the technology continues with dimensional scaling and implementation of porous ultralow- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> materials.

Mechanical Scaling Trends and Methods to Improve Reliability of Packaged Interconnect Structures

AbstractLow dielectric constant (low-k) materials are currently being incorporated into advanced microelectronic devices to improve or maintain performance. As the dielectric constant is reduced, so are its mechanical properties. These reduced properties have recently been related to chip-package interaction (CPI) failures. Significant effort has focused on eliminating CPI failures through engineering of copper crackstop structures. However, published data suggests that crackstop engineering needs to occur at each technology node to ensure CPI reliability. In this study, the focus is on repairing interfacial delaminations with chemistry specific coupling agents rather than attempting to stop them with a specially designed crackstop structure. Critical adhesion values and corrosion resistance of the repaired interfaces are compared to the original interface. The application of the repair chemistry in an integrated structure is discussed along with the potential impact on reliability.