Chip-on-board Light-emitting Diodes Research Articles

Effect of refractive index of packaging materials on the light extraction efficiency of COB-LEDs with millilens array.

Lens arrays are introduced to diminish the total internal reflection (TIR) that happens at chip-encapsulant and encapsulant-air interfaces of chip-on-board light-emitting diodes (COB-LEDs), so as to improve the light extraction efficiency (LEE) of the COB-LEDs. However, the LEE of COB-LEDs with lens array depends on the refractive index of the encapsulant layer nencap and lens array nlens, which was rarely concerned so far. Optical simulations based on a Monte Carlo ray tracing method, and experiments were conducted to investigate the effect of nencap and nlens on the LEE of COB-LEDs with millilens array. The simulated results show that the TIR at chip-encapsulant, encapsulant-lens, and lens-air interfaces can be significantly diminished by regulating the nencap and nlens, and the LEE of COB-LEDs decreases as the refractive difference of encapsulant layer and lens array |nlens-nencap| increases. Compared to the COB-LEDs with only a flat encapsulant layer, the LEEs of blue and white COB-LEDs with nlens=nencap=nITO=2 are enhanced by 246.2% and 50.6%, where nITO is the refractive index of the top layer of the conventional LED chip. The experimental results agree well with the simulated results with normalized LEE deviation within 7.3%.

A Simple Method to Realize Millilens Array on Encapsulant Layer for Enhancing Light Efficiency of COB-LEDs

The chip-on-board light-emitting diodes (COB-LEDs) present low light efficiency due to the total internal reflection (TIR) at the flat encapsulant–air interface. In this study, a simple method based on complementary printing was proposed to realize the millilens array on the flat encapsulant layer to diminish the TIR effect, and thereby improve the light efficiency of the COB-LEDs. Experiments and optical simulation based on the Monte Carlo ray-tracing method were conducted to investigate the effect of the lens curvature $\theta $ , lens radius ${R}$ , and lens spacing ${D}$ on the light efficiency of the COB-LEDs. The results show that the light efficiency of the COB-LEDs increases with ${R}$ and decreases with ${D}$ , and COB-LEDs with hemispherical lens arrays ( ${\theta = }90^{\circ }$ ) have the highest light efficiency when ${R}$ and ${D}$ are fixed. Compared with the conventional COB-LEDs with a flat encapsulant, closely arranged hemispherical lens arrays with an ${R}$ of 0.5, 1, and 1.5 mm enhance the light efficiency of the blue COB-LEDs by 87.56%, 90.62%, and 95.73% and enhance the light efficiency of ~6000-K white COB-LEDs by 17.24%, 18.86%, and 20.33%, respectively.

Cylindrical Tuber Encapsulant Layer Realization by Patterned Surface for Chip-on-Board Light-Emitting Diodes Packaging

In this study, we realized a cylindrical tuber silicone layer for improving the light efficiency of chip-on-board light-emitting diodes (COB-LEDs) by fabricating patterned LED substrate with both silicone-wetting and silicone-repellency surfaces. To realize silicone-repellency surface, low surface energy modified nanosilica particles were prepared and deposited on the LED substrate to form porous hierarchical structure. Light efficiency enhancement for blue light COB-LEDs with pure cylindrical tuber silicone layer and white light COB-LEDs with phosphor–silicone composite layer was studied. The results show that for blue light COB-LEDs with pure cylindrical tuber silicone layer, the light efficiency increases with the contact angle and a highest light efficiency enhancement of 62.6% was achieved at 90 deg when compared to the flat silicone layer. For white light COB-LEDs at correlated color temperature (CCT) of ∼5500 K, the cylindrical tuber silicone layer enhances the light efficiency by 13.6% when compared to the conventional flat phosphor layer.

A Facile Approach to Fabricate Patterned Surfaces for Enhancing Light Efficiency of COB-LEDs

Light efficiency of chip-on-board light-emitting diodes (COB-LEDs) is much lower than the single-chip packaging LEDs due to its flat phosphor layer, and hemispherical phosphor layer realization is a great challenge in COB-LEDs packaging due to the low surface tension of the phosphor gel. In this paper, we demonstrated a facile method to fabricate patterned surfaces to deal with this challenge. First, nanosilica (NS) particles with average diameter of 70 nm were fabricated by hydrolyzing the tetraethoxysilane and further modified by 1H,1H,2H,2H-perfluorooctyl-trichlorosilane, then patterned surfaces were fabricated by introducing a tailored template into the NS coating process. The results show that the NS coated surfaces display repellency to the water and phosphor gel with porous lotus leaf-like hierarchical structure, when the particle deposition density (PDD) of the NS particles increases from 0 to 6 g/m2, the contact angle (CA) of water increases from 34° to 161°, and the CA of phosphor gel increases from 22° to 145°. Hemispherical phosphor layer was achieved with the patterned surfaces when the PDD is 1.5 g/m2. Compared to the conventional flat phosphor layer, the hemispherical phosphor layer enhances the light efficiency by 11.74% and 14.52% for 4000 and 5000 K COB-LEDs.

Optimization of the thermal distribution of multi-chip LED package

Light emitting diodes (LEDs) are fascinating a thermal problem due to the increase of their junction temperature. Thermal management of LED module is the key to improve the performances of LED. In this paper, a three dimensional thermal analysis of 3.5W multi-chip COB (chip-on-board) LED package was developed using COMSOL Multiphysics®. An optimization of the number of LED-chip and their disposition on different substrate was carried out. The results showed that the interference of heat spreading in substrate level, the junction temperature and the thermal resistance of the LED lamp decreased well with the increase of gaps between chips and reached an optimal value. A correlation of optimal pitch was determined as a function of chip number, chip size and substrate size. It was found that using the optimal multi-chip model instead of one LED-chip leads to a decrease of the junction temperature about 12.54%, 14.96% and 17.1% for AlN, Al2O3 and IMS substrates respectively.

Enhanced light extraction efficiency of chip-on board light-emitting diodes through micro-lens array fabricated by ion wind

Low light extraction efficiency (LEE) is a key challenge of chip-on board (COB) packaging light-emitting diodes (LEDs). In this paper, a facile preparation of micro-lens array was proposed based on the ion wind patterning. The geometries and sizes of the micro-lens arrays were controlled through adjusting the voltage parameter of the ion wind generation. Consequently, the micro-lens array with the diameter of 180µm and the gap distance of 15µm has been fabricated. Benefitting from this micro-lens array, the LEE of COB packaging LEDs was enhanced by 9%. This facile fabrication of micro-lens array would be a promising method to improve the LEE of COB packaging LEDs.

Thermal Analysis of High-Power Multichip COB Light-Emitting Diodes With Different Chip Sizes

This paper demonstrates the thermal analysis of high-power light-emitting diodes (LEDs) with various chip sizes, in the same chip-on-board (COB) package and with the same total chip size and input power. The 4-, 9-, 25-, and 100-chip multichip COB LEDs with chip-side lengths of 1500, 1000, 600, and 300 $\mu $ m were used. The simulation results indicate that the maximal junction temperature of the multichip COB LEDs increased as the number of chips in the multichip COB LED decreased. In addition, with the same input power, the difference between the maximal and minimal junction temperatures of the multichip COB LED increased as the number of chips in multichip COB LEDs increased. That is, if the multichip COB LED contains a few number of large chips, the output power of each chip will drop but uniform owing to the high junction temperature and low temperature difference. Oppositely, if the multichip COB LED contains a lot of small chips, the output power of the chips at the corners will be higher than other chips, but the output power of each chip will be nonuniform owing to the nonuniform junction temperature distribution.