A Facile Approach to Fabricate Patterned Surfaces for Enhancing Light Efficiency of COB-LEDs

Abstract

Light efficiency of chip-on-board light-emitting diodes (COB-LEDs) is much lower than the single-chip packaging LEDs due to its flat phosphor layer, and hemispherical phosphor layer realization is a great challenge in COB-LEDs packaging due to the low surface tension of the phosphor gel. In this paper, we demonstrated a facile method to fabricate patterned surfaces to deal with this challenge. First, nanosilica (NS) particles with average diameter of 70 nm were fabricated by hydrolyzing the tetraethoxysilane and further modified by 1H,1H,2H,2H-perfluorooctyl-trichlorosilane, then patterned surfaces were fabricated by introducing a tailored template into the NS coating process. The results show that the NS coated surfaces display repellency to the water and phosphor gel with porous lotus leaf-like hierarchical structure, when the particle deposition density (PDD) of the NS particles increases from 0 to 6 g/m2, the contact angle (CA) of water increases from 34° to 161°, and the CA of phosphor gel increases from 22° to 145°. Hemispherical phosphor layer was achieved with the patterned surfaces when the PDD is 1.5 g/m2. Compared to the conventional flat phosphor layer, the hemispherical phosphor layer enhances the light efficiency by 11.74% and 14.52% for 4000 and 5000 K COB-LEDs.