Chip Measurement Research Articles

A 2.2-$\mu\hbox{m}$-Pitch Single-Transistor Charge-Modulation Pixel in a 0.13-$\mu\hbox{m}$ CMOS Process

This paper presents the investigation of a 2.2-mum-pitch single-transistor pixel designed in a 0.13-mum CMOS process. Based on charge-induced potential variation of the floating-body of the transistor, this single pixel device can be operated to perform photodetection, charge integration, signal readout, and reset. The main electrical characteristics of the pixel are evaluated by device modeling and simulations as well as measurements of test chips. With optimization of process and electrical parameters, testing results show a conversion factor of 47 muV/hole, a charge-handling capability of 3500 holes, a temporal noise of four holes, and a dynamic range of 40 dB.

A 12-Gb/s DEMUX Implemented With SiGe High-Speed FPGA Circuits

A 7-12-Gb/s demultiplexer implemented with circuits for a high-speed field-programmable gate array (FPGA) is introduced in this paper. Since the first FPGA was released by Xilinx in 1985, FPGAs have become denser and more powerful. The first FPGA that operates in the microwave range was designed in 2000. Various methods, such as a new basic cell structure and multimode routing, are used to make that design faster and less power consuming. Sequential logic functions are analyzed and tested in this paper with a DEMUX implementation using these high-speed FPGA circuits. A chip measurement has shown that the FPGA can operate at a 12-GHz system clock when configured to perform sequential logic. A DEMUX that operates at 12 Gb/s is used here to demonstrate the potential for high-performance and low-power FPGA features.

A 12-Gb/s DEMUX Implemented With SiGe High-Speed FPGA Circuits

A 7-12-Gb/s demultiplexer implemented with circuits for a high-speed field-programmable gate array (FPGA) is introduced in this paper. Since the first FPGA was released by Xilinx in 1985, FPGAs have become denser and more powerful. The first FPGA that operates in the microwave range was designed in 2000. Various methods, such as a new basic cell structure and multimode routing, are used to make that design faster and less power consuming. Sequential logic functions are analyzed and tested in this paper with a DEMUX implementation using these high-speed FPGA circuits. A chip measurement has shown that the FPGA can operate at a 12-GHz system clock when configured to perform sequential logic. A DEMUX that operates at 12 Gb/s is used here to demonstrate the potential for high-performance and low-power FPGA features.

A 120-dB Dynamic Range CMOS Image Sensor With Programmable Power Responsivity

A high dynamic range CMOS image sensor providing a user-programmable power responsivity curve is presented. Each pixel integrates, besides a 4T active pixel structure, a voltage comparator and an analog memory to implement a time-to-saturation scheme while also providing the standard integrated photo-current signal. The sensor generates two 10-bit analog outputs allowing a typical dynamic range exceeding 120 dB with a temporal noise lower than 0.13% and a fixed pattern noise of 0.4% (1.7%) of the total signal swing (2 V) at low (high) irradiance without any external calibration procedures. A 140 times 140-pixel array has been fabricated in a 0.35-mum, two-poly four-metal (2P4M), 3.3-V standard CMOS technology. The chip measures 3.9 times 4.6 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> with a pixel pitch of 15 mum and a fill factor of 20%.

OS5-3-3 Warpage measurement of a LCD chip using projection speckle correlation method and microscopic interferometry

OS5-3-3 Warpage measurement of a LCD chip using projection speckle correlation method and microscopic interferometry

A blue-violet enhanced BDJ photodetector and its applications in the probe chip measurements of the LEDs for solid-state lighting

A blue-violet enhanced buried double p–n junction (BDJ) photodetector with its characteristics is reported in this manuscript. It was fabricated on high resistivity float-zone silicon substrate by using ion implantation and exhibits low leakage currents. It can measure both the light intensity as a photometric detector and the wavelength of quasi-monochrome light as a wavelength sensor simultaneously. It was optimized to operate at wavelength from 380 nm to 780 nm in which the light emitting diodes (LEDs) for solid-state lighting is most interested. The resolution for the wavelength measurement of the photodetector is better than 1 nm. The probe chip tests of violet, blue, green and red LED chips have been demonstrated using the fabricated detector. This simple, fast and reliable method provides an alternative to low cost and fast examination technique for LED chips in vast production.

A 510‐kb SOG‐DRAM for mobile displays with embedded frame memories

Abstract— A system‐on‐glass (SOG) dynamic random access memory (DRAM), which enables the implementation of frame‐memory‐integrated displays, has been developed. A dynamic one‐transistor‐one‐capacitor memory cell, which has a data retention time of over 16.6 msec, and a compression/decompression (CODEC) circuit were developed to reduce the layout area and power. The CODEC enables an 18‐bit/pixel color display, while reducing the memory capacity from 18 to 12 bits/pixel. A frame‐memory macro was created by combining the SOG‐DRAM with an embedded controller that enables independent access for writing and reading. Its operation was verified by chip measurement and demonstration as a frame‐memory operation of 262k‐color QCIF+ displays. The work reported in this paper was the first step to creating a Zero‐Chip Display with an integrated frame memory, and it proved the concept was feasible.

Multi-Ported Register File for Reducing the Impact of PVT Variation

We have developed a 32-bit, 32-word, and 9-read, 7-write ported register file. This register file has several circuits and techniques for reducing the impact of process variation that is marked in recent process technologies, voltage variation, and temperature variation, so called PVT variation. We describe these circuits and techniques in detail, and confirm their effects by simulation and measurement of the test chip.

SU-FF-J-76: Minimally-Invasive Intraoperative Radiotherapy (MIR): Technique Development for Treatment of Canine Bladder Cancer

Purpose: To develop, model, and quantify the dose reduction on critical structures using Minimally-Invasive Intraoperative Radiotherapy (MIR) for the treatment of canine bladder cancer, and develop the technique for laparoscopic placement of the custom tissue expander. Method and Materials: A custom tissue expander was constructed and implanted between the bladder and descending colon of three Beagle cadavers. Two of the implants were placed via laparotomy, and one was laparoscopically placed. The cadavers were positioned in a body fix mold, and CT scanned with the custom tissue expander inflated with saline solution and deflated. A radiation therapy treatment plan was constructed on the tomotherapy treatment planning system for the inflated and deflated CT scans of each cadaver. TLD chips were placed on the bladder and colon side of the laparoscopically placed tissue expander. Pre-treatment target localization was accomplished by using the onboard MVCT of tomotherapy. Both inflated and deflated treatment plans for one fraction of the laparoscopically placed cadaver were delivered. Results: Keeping the dose to the bladder fixed, the average dose reduction when the tissue expander is inflated for the colon is 42.7%, spine is 38.7%, left kidney is 50.52%, and right kidney is 31.9%. A significant maximum dose reduction to these structures is also achieved. TLD chip measurements on either side of the inflated tissue expander showed a dose reduction of 55.1%. Conclusion: The cadaver studies evaluated indicate the potential for a clinically significant dose reduction to the colon, spine, left and right kidneys using MIR. An effective laparoscopic technique was developed to allow for the quick placement of the custom tissue expander in the abdominal cavity with minimal incisions. Conflict of Interest: This work was partially supported by a grant from the NIH (P01 CA088960) and a contract from TomoTherapy Inc.

24.4: A 510-Kb SOG-DRAM for Frame-Memory-Integrated Displays

A system-on-glass (SOG) DRAM intended for integrated frame-memories of 262k-color QCIF+ displays has been developed. An integrated codec circuit reduces the number of memory cells and layout area by a factor of 2/3. By combining the SOG-DRAM, which has a data retention time of over 16.6 ms, with an embedded controller that enables simultaneous access for writing and reading, a frame-memory has been created. The operation was verified by chip measurement and demonstration.

An on-chip active decoupling circuit to suppress crosstalk in deep-submicron CMOS mixed-signal SoCs

A decoupling circuit using an operational amplifier is proposed to suppress substrate crosstalk in mixed-signal system-on-chip (SoC) devices. It overcomes the parasitic inductance problem of on-chip capacitor decoupling. The effect of the proposed decoupling circuit is not limited by parasitic fine impedance. A 0.13-/spl mu/m CMOS test chip showed that substrate noise at frequencies from 40 MHz to 1 GHz was incrementally suppressed by sequentially activating three of the proposed circuits in parallel. The power dissipation of each circuit was 3.3 mW at a 1.0-V power supply. The test chip measurement showed that the proposed decoupling reduced crosstalk by 31% at 200 MHz, whereas it was reduced by 4.4% with capacitor decoupling. This 7:1 ratio, or 17 dB, corresponds to the gain of the opamp. Design of the opamp and its feedback loop for active decoupling is simple, making the opamp useful for SoC applications.

Comparative Assessment of the Force Prediction Abilities of Some Single Edge Orthogonal Cutting Models over Diverse Data

The relative force prediction abilities of some well-known ANN-based, empirical and analytical models are assessed against several independent datasets by taking the rms error of cutting and thrust forces over all the datasets as the criterion. Progressing beyond mere data analysis, attention is paid to issues concerning how the model parameters themselves could be numerically modeled. A methodology for avoiding the need for measuring the shear angle, φ, is also developed. Model coefficients are estimated through nonlinear constrained optimization techniques. For estimating φ, the fractional variation of an idealized material invariant such as the mean shear stress, τ, on the shear plane is minimized subject to Hill's classical constraints. Several hitherto unknown insights regarding the relative effectiveness of each of the models have emerged. For example, it is found that the φ-values estimated from the measured forces alone are superior to those determined from chip measurements in the traditional manner.

Noise Determination in Differential Pair-Based Second Generation Current Conveyors

The aim of this paper is to give simple design guidelines for the noise evaluation in differential pair-based second generation current conveyors (CCIIs). Input noise voltage and current have been expressed in terms of some well known constants and MOS gm values, so allowing a very fast estimation of the noise level. The presented theory has been verified, as an example, on two fabricated low voltage low power CCII topologies. Theoretical values, simulations and on chip measurements are also shown and their good agreement confirms the validity of the presented idea.

A 5–10 GHz SiGe BiCMOS FPGA with new configurable logic block

This paper presents a new multiplexer based FPGA, which can operate at a clock frequency of 5–10 GHz. Redundant switches on the original signal paths are removed improving the performance. The configurable logic blocks (CLBs) power is greatly reduced by using a revised multiplexer structure and turning off unused cells dynamically. More routing capabilities are provided with more inputs/outputs in each direction than similar designs. A chip consisting of four FPGA ring oscillators was fabricated. The Spice simulation results and chip measurements are presented.

Toward CNN Chip-Specific Robustness

The promising potential of cellular neural networks (CNN) has resulted in the development of several template design methods. The CNN universal machine (CNN-UM), a programmable CNN, has made it possible to create image-processing algorithms that run on this platform. However, very large-scale integration implementations of CNN-UMs presented parameter deviations that do not occur on ideal CNN structures. Consequently, new design methods were developed aiming at more robust templates. Although these new templates were indeed more robust, erroneous behavior can still be observed. An alternative for chip-independent robustness is chip-specific optimization, where the template is targeted to an individual chip. This paper describes a solution proposal in this sense to automatically tune templates in order to make the chip react as an ideal CNN structure. The approach uses measurements of actual CNN-UM chips as part of the cost function for a global optimization method to find an optimal template given an initial approximation. Further improvements are achieved by generating chip-specific robust templates by doing a search for the best template among the optimal ones. The tuned templates are therefore customized versions that are expected to be much less sensitive to imperfections on the operation of CNN-UM chips. Results are presented for the binary and grayscale cases, including the case of grayscale output. It is expected that as this technique matures, it will give CNN-UM chips enough reliability to compete with digital systems in terms of robustness in addition to advantages of speed.

A High-Speed 128-kb MRAM Core for Future Universal Memory Applications

A 128-kb magnetic random access memory (MRAM) test chip has been fabricated utilizing, for the first time, a 0.18-/spl mu/m V/sub DD/=1.8 V logic process technology with Cu metallization. The presented design uses a 1.4-/spl mu/m/sup 2/ one-transistor/one-magnetic tunnel junction (1T1MTJ) cell and features a symmetrical high-speed sensing architecture using complementary reference cells and configurable load devices. Extrapolations from test chip measurements and circuit assessments predict a 5-ns random array read access time and random write operations with <5-ns write pulse width.

On-line spectroscopic measurements of wood chips before a continuous digester

A VIS spectrometer was evaluated during 25 days of on-line operation. The spectrometer was installed above a conveyor belt carrying softwood chips to a continuous digester that was charged with 100 tonnes chips/h. We found that VIS spectroscopy can be used on-line both to predict chip properties and to monitor a continuous digester. Prediction models for pine, bark and dry content were made using partial least square (PLS) regression models. The prediction models were based on data from a designed experiment that was performed in the lab before the on-line installation. Spectral information taken from the VIS range can be used for monitoring the digester, as the information correlates well to process variables. For 3 days, an NIR spectrometer, calibrated via a designed experiment to make the same predictions as did the VIS spectrometer, was also installed at the conveyor belt. The VIS and NIR predictions proved to be similar.

A foveated-structure CMOS retina chip for edge detection with local light adaptation

A foveated-structure CMOS retina chip for edge detection with local light adaptation is presented. The functions of photoreceptors, horizontal cells, and bipolar cells in the human retina are transformed to a simple equivalent circuit for detecting the edge of an input image. The unit pixel of the chip consists of only four MOSFETs and two photo-transistors. A 32×32 foveated-structure local light-adaptive retina chip for edge detection has been designed and fabricated using 0.6 μm double-poly triple-metal CMOS process. The fabricated retina chip measures 8 mm ×8 mm and could detect the edges of an input image with a wide range of light intensity. It is anticipated that this local light-adaptive CMOS retina chip could find applications in the area of active vision systems for target tracking and recognition.

Electrochemiluminescent biosensors array for the concomitant detection of choline, glucose, glutamate, lactate, lysine and urate

A multifunctional bio-sensing chip was designed based on the electrochemiluminescent (ECL) detection of enzymatically produced hydrogen peroxide. Six different oxidases specific for choline, glucose, glutamate, lactate, lysine and urate were non-covalently immobilised on imidodiacetic acid chelating beads (glucose oxidase only) or on diethylaminoethyl (DEAE) anion exchanger beads, and spotted on the surface of a glassy carbon foil (25 mm 2 square), entrapped in PVA-SbQ photopolymer. The chip measurement was achieved by applying during 3 min a +850 mV potential between the glassy carbon electrode and a platinum pseudo-reference, while capturing a numeric image of the multifunctional bio-sensing chip with a CCD camera. The use of luminol supporting beads (DEAE–Sepharose) included in the sensing layer was shown to enable the achievement of spatially well defined signals, and to solve the hydrogen peroxide parasite signal which appeared between contiguous spots using luminol free in solution. The detection limits of the different biosensor were found to be 1 μM for glutamate, lysine and uric acid, 20 μM for glucose and 2 μM for choline and lactate. The detection ranges were 1–25 μM (uric acid), 1 μM–0.5 mM (glutamate and lysine), 20 μM–2 mM (glucose) and 2 μM–0.2 mM (choline and lactate). The ECL chip was used for the detection of glucose, lactate and uric acid in human serum matrix. Good correlations between measured and expected values were found without the need of internal calibration of the sample, demonstrating the potentiality of the ECL multifunctional bio-sensing chip.

Linearity performance comparison of cascode current source and single-device current source IDPs; analyses, simulations and measurements

The input differential pair (IDP) is usually a major source of nonlinear distortion in any op-amp. This is especially true if the input signal has a large common-mode component, as is the case when an op-amp functions as a unity-gain buffer or as part of a single-ended sample-hold (S/H) circuit. In this paper, we analyse the distortion of the commonly used cascode current source IDP structure and explain the sources of its nonlinear behaviour. Next, a special design technique is proposed which enhances the linearity of IDPs. The circuit uses a single device current source that has the same channel length while its width is double those of IDP devices. Theoretical analysis, as well as simulation and experimental results, is given to confirm the improved linearity of a unity gain buffer. Simulations predict improvements up to 20 dB. 15 dB total harmonic distortion (THD) reduction was also achieved for a 15 MHz input signal based on measurement of a test chip. The method is valuable as power supply voltages shrink, and the design offers extra voltage headroom at input.