Chip Dicing Research Articles

INCREASE PRODUCTION OUTPUT ON TWA 1342 MACHINE WITH OVERALL EQUIPMENT EFFECTIVENESS (OEE) METHOD (CASE STUDY: PT XYZ BATAM)

PT XYZ Batam is a manufacturing company that produces NTC (Negative Temperature Coefficient) Sensors. This company has a Chip Dicing Department which is cutting the NTC substrate into chips and then measuring process, measuring process is checking process based on the chip resistance value by the TWA 1342 machine.Currently, the output of measuring process is not stable, so this study aims to determine the cause of low output and how to increase production output on the TWA 1342 machine with Overall Equipment Effectiveness (OEE) method. The results obtained based on calculations on the TWA 1342 machine are : availability value 95.12%, Performance value 85.06%, Quality value 98.97% and OEE value 80.08%.Based on the Pareto chart, the cause of output target being not achieved was due to a filter was not suitable for use, because there were tears on the surface of the filter so the dirt was not filtered properly. And the action taken based on the fishbone diagram analysis is to replace the filter periodically and control it by having a filter change record.After the corrective steps have been taken, the changes in the OEE value on the TWA 1342 machine for one week of observation are as follows: Availability value 99.69%, Performance value 98.10%, Quality value 99.15%. And the OEE value is 96.96%. The percentage of the total output during the week of observation after corrective steps was taken is 98.10%. Where there is an increase in output of 13.04%.

Laser‐Based Micro/Nano‐Processing Techniques for Microscale LEDs and Full‐Color Displays

AbstractMicro light‐emitting diode (Micro‐LED) display is an emerging display technology thanks to its high brightness, fast switching speed, and low power consumption. The commercialization of this technique is being explored by developing advanced processing techniques on an industrial scale. Recent ground‐breaking advances in the manufacture of Micro‐LEDs are mainly based on powerful laser micro/nano‐processing techniques with the unique ability to fabricate materials, structures and devices with the advantages of non‐contacting processing, high efficiency, adjustable coverage from micro‐ to macroscale and the compatibility with organic and inorganic materials. This paper categorizes, reviews and analyzes the main challenges and technical solutions in the Micro‐LED displays by various laser manufacturing processes, covering chip dicing, geometry shaping, laser annealing, laser lift‐off (LLO), laser‐based Micro‐LED transfer, laser‐assist bonding (LAB) and laser repair. The fundamental principles of these techniques are discussed along with their basic mechanisms, followed by an exploration of the latest progress in the field. Finally, a detailed analysis of the advantages and disadvantages of these techniques is given, and the future research directions of laser techniques in Micro‐LED display are discussed.

Reliability improvements of thin film platinum resistors on wafer-level and micro-hotplates at stress temperatures in the range of 140–290 °C

In this work, we present the improvement of thermal long-term reliability of platinum resistors through transition from a quasi-stoichiometric SiO2 layer to silicon-rich SiOx cover layers. The physical effects were investigated on a platinum meander test structure using a wafer-level based approach. As a result, reliability can be studied simultaneously on several hundreds of chips with a great statistical certainty. In addition, possible influences of chip dicing and packaging technology can be avoided. The activation energy for drift is extracted from a linear fit to the Arrhenius diagram. Furthermore, a comparison of drift data with an analytical equation is done as proposed in literature. Investigations with resistors on fabricated micro-hotplates exemplify the validity of improving the long-term reliability even on device-level.

48 × 48 pixelated addressable full-color micro display based on flip-chip micro LEDs.

This paper reports on the design and fabrication of a ${48} \times {48}$48×48 full-color pixelated addressable light-emitting diode on silicon (LEDoS) micro display. The metallization pattern was designed and fabricated on a silicon substrate, while red, green, and blue monochromatic micro LEDs were integrated on the silicon substrate using transfer printing. The red, green, and blue micro LEDs are flip-chip structures in which red micro LEDs were fabricated using substrate transfer, mesa etching, metal deposition, and chip dicing. The integration process does not require wire bonding, which reduces the full-color pixel size and increases the integration speed. The LEDoS micro display can be addressed individually for each LED pixel and display representative patterns.

Detailed Investgations of Inner Cavity Pressure of MEMS Devices Sealed by Wafer Bonding

Introduction State of the art MEMS devices, such as inertial sensors, consist of very fragile, sensitive elements which should be protected by a cap at the wafer level, to allow standard chip dicing and assembly technologies. Typically, wafer bonding is used for this capping. Since, in the bonding process, the type and pressure of the gas can be controlled, the sealed gas in the MEMS device can be tuned and used for device functionality. This is, for example, very important for resonant MEMS devices such as gyroscopes. These essentially require a high Q-factor, which can only be achieved at low cavity pressures. The actual sealed pressure depends on many factors, such as the chamber pressure during bonding, out-gassing from the bonding material (e.g. glass frit), as well as from the sealing behaviour of the bonding process used. Concepts for MEMS Inner Pressure Measurement At the last ECS Semiconductor Wafer Bonding Symposium in 2012, an approach was introduced for measuring the MEMS cavity inner pressure using the thermal conductivity of the sealed gas, which is strongly dependent on the absolute pressure [1]. While this type of measurement principle had already been previously reported in the literature [2], a special test structure, adapted to a MEMS foundry surface micromachining process [3] for inertial sensors, was described, which allows high-resolution measurement. The vehicle itself is very small and can be easily integrated into mask sets as special test elements and even into functional chips for lifetime monitoring. The measurement principle is based on a heater and temperature measurement resistors which can detect the amount of heat transferred from the heater and, by this, measure the inner cavity pressure. The measurement principle was the subject of the original publication [1], but this paper reports various new measurement results. Results of Inner Cavity Pressure Measurement In the MEMS Foundry Open Platform technology [3] the cavity pressure measurement device is fabricated and used for glass frit bonding which is used to seal the devices (gyroscopes or acceleration sensors). This bonding process is still very attractive regarding cost and process integration, since almost any surface layer and surface profile arising from metal wiring can be bonded and hermetically sealed. However, the glass frit bonding shows some specific behaviour regarding the sealed pressure, since a small amount of outgassing of remaining organics results a slightly higher pressure in the sealed MEMS cavity than set by the pressure in the wafer bonding equipment chamber. Hence, the essential question is: what pressure is actually sealed in the MEMS device? This is also very interesting in relation to the bonding temperature, which is at ~450°C, so that the sealed gas is cooled down after bonding which reduces the sealed pressure at room temperature by a factor of ~2.7, related to the classical thermodynamic ideal gas conditions. These questions were investigated by applying different pressures in the bonding chamber, and measuring the MEMS inner cavity pressure after finishing the glass frit wafer bonding and cooling down the wafer stack.These investigations have confirmed the theory and helped to set up the correct bond chamber pressure for achieving the targeted MEMS cavity pressure. The glass frit material is known to be hygroscopic based on its glass composition, so that it can absorb humidity from air if it is stored after its full glazing cycle. The relevance of this phenomenon was investigated using the inner cavity pressure measurement structure. Cap wafers with completely-processed glass frit were stored in air for different times, and, indeed, different MEMS cavity pressures were measured after bonding. With longer storage time, humidity is absorbed into the glass which outgases into the cavity during bonding, and increases the cavity pressure. Conclusions The heat-transfer-based inner cavity measurement structure is well-suited for monitoring the sealed pressure of MEMS structures in production processes, reliability testing and over the lifetime, as well as for in-depth investigation of wafer bonding processes – further examples will be reported in the full paper.

Material and Structure Designs for Reliable Quad-Flat-Package for Scaled-Down Ultralarge-Scale Integrations With Porous Low-$k/{\rm Cu}$ Interconnects

Reliability of a quad-flat-package (QFP) with a circuit-under-pad (CUP) structure is investigated for Cu interconnects with porous low dielectric constant (low-k) films in scaled-down ultralarge-scale integrations. The following experimental factors are discussed: 1) low-k material properties and their stacking structures; 2) CUP structure; and 3) mold compound material properties. The QFP characteristics are analyzed after chip dicing and Ag wire bonding, as well as after molding. Higher adhesion strength of porous low-k film to SiCN cap dielectrics and rigid Cu-anchored CUP structure can achieve highly reliable QFP packaging. A lower coefficient of thermal expansion (CTE) of the molding compound is also found to be effective in eliminating low-k delamination during thermal cycle test because it can reduce the stress at the cracking position. The adhesion-promoting porous SiOCH film with the Cu-anchored CUP in a low-CTE mold is a promising system to realize a reliable QFP with no low-k delamination, passing electrical tests after the pressure-cooker test and high-temperature storage test.

Advanced TSV Copper Electrodeposition for 3D Interconnect Applications

Robust and manufacturable processes are needed to enable a smoother and faster transfer of TSV technology from development to production. There are several steps involved with TSV technology application. Either if it is done before or after thinning the wafer, as a via first, middle or via last approach, the main steps are: via etching, lining with insulator/barrier and copper seed, deep via fill and chemical mechanical planarization (CMP), chip dicing and stacking. Deep via fill is one of thee most critical steps in forming the TSV electrodes, and copper electrodeposition process has been identified to be the most appropriate and cost effective method of filling the vias. Various critical factors with significant effect on the process performance were found: seed layer uniformity, via profile and size, stability and performance of the chemicals and equipment design. The amount and quality of the copper at the top of the vias and over the entire surface of the wafer is very important for the CMP processing. A more uniform deposition and lower overburden could significantly decrease the complexity and cost of the CMP step. The copper thickness profile between deposition and CMP can be cross-optimized to reduce dishing, increase throughput and reduce cost. This paper will focus on the deep via fill, the critical factors associated with this step and integration aspects of Cu TSV deposition step that need to be taken in consideration for successful application of this technology. A significant amount of work has been performed to develop processes that can successfully fill features of various sizes in a cost effective way. Some of the chemistries available commercially today, although have very good super-fill characteristics, have the disadvantage of forming nodular and high-stress deposits which could have a negative impact on CMP processing. An innovative process with strong bottom-up capability that significantly reduces the overburden while increasing the speed of deposition has been developed at Semitool and the characteristics of this process and advantages over previous generation processes will be presented. The effect of copper stress and copper extrusion observed during annealing step as well as approaches taken to minimize this effect will be described.

Interfacing microfluidics to LDI-MS by automatic robotic spotting

We developed a method of interfacing microfluidics with mass spectrometry (MS) using a robotic spotting system to automate the contact spotting process. We demonstrate that direct and automated spotting of analyte from multichannel microfluidic chips to a custom microstructured MALDI target plate was a simple, robust, and high-throughput method for interfacing parallel microchannels using matrix-assisted laser desorption/ionization mass spectrometry (MALDI-MS). Using thermoplastic cyclic olefin copolymer (COC) polymer microfluidic chips containing eight parallel 100 μm × 46 μm microchannels connected to a single input port, spotting volume repeatability and MALDI-MS signal uniformity are evaluated for a panel of sample peptides. The COC microfluidic chips were fabricated by hot embossing and solvent bonding techniques followed by chip dicing to create open ends for MS interfacing. Using the automatic robotic spotting approach, microfluidic chip-based reversed-phase liquid chromatography (RPLC) separations were interfaced with electrochemically etched nanofilament silicon (nSi) target substrate, demonstrating the potential of this approach toward chip-based microfluidic separation coupled with matrix-free laser desorption/ionization mass spectrometry.

Study on the Effects of Wafer Thinning and Dicing on Chip Strength

Die cracking is an annoying problem in the packaging industry. In this paper, we identified the weak regions, in terms of mechanical strength, in chips in a semiconductor wafer using the three-point bending test. The weak regions were observed in two sectors approximately 45/spl deg/ wide, axisymmetric to the wafer center. The strength of the chips within these weak regions was about 30%-35% lower than the average chip strength of the whole wafer. The existence of these weak regions was related to spiral grinding marks, which, in turn, were formed by backside mechanical grinding. The probability distributions of the chip strength and the chip fragmentary pattern confirmed this relationship. When wafers were mechanically ground until they were 50-/spl mu/m thick, chip warpage was found to be oriented to the direction of the grinding marks. Meanwhile, by slowing the mechanical grinding speed by 50%, we were able to increase the average chip strength by 56%. Either plasma etching or polishing after mechanical grinding eliminated the weak regions, and the optimal amount of mechanical grinding and the polishing depths were observed, beyond which the chip strength would not increase. On the other hand, a preprocess for blunting a new saw blade for chip dicing was found to be essential as the chip strength increased five-fold, whereas increasing the dicing speed or using dual saw instead of a single saw had only small effects on the chip strength degradation.

A hybrid wafer-dicing process for GaAs MMIC production

A dicing process for GaAs MMIC (monolithic microwave integrated circuit) wafers using spin-on wax for wafer mounting and a hybrid process of wet chemical etching/mechanical sawing for chip dicing is described. This process minimizes ragged chip edges and reduces generation of microcracks in addition to the elimination of the plated gold burrs on the backside of the diced MMIC chips. This process gives a uniformity of -3 mu m across a 2-in wafer following the completion of the whole backside process. This GaAs chip dicing technique is amenable to production because it exhibits both a very high chip yield (>90%) and nearly flawless edges.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>