Chip Cost Research Articles

Color Measurement and Analysis of Fruit with a Battery-Less NFC Sensor.

This paper presents a color-based classification system for grading the ripeness of fruit using a battery-less Near Field Communication (NFC) tag. The tag consists of a color sensor connected to a low-power microcontroller that is connected to an NFC chip. The tag is powered by the energy harvested from the magnetic field generated by a commercial smartphone used as a reader. The raw RGB color data measured by the colorimeter is converted to HSV (hue, saturation, value) color space. The hue angle and saturation are used as features for classification. Different classification algorithms are compared for classifying the ripeness of different fruits in order to show the robustness of the system. The low cost of NFC chips means that tags with sensing capability can be manufactured economically. In addition, nowadays, most commercial smartphones have NFC capability and thus a specific reader is not necessary. The measurement of different samples obtained on different days is used to train the classification algorithms. The results of training the classifiers have been saved to the cloud. A mobile application has been developed for the prediction based on a table-based method, where the boundary decision is downloaded from a cloud service for each product. High accuracy, between 80 and 93%, is obtained depending on the kind of fruit and the algorithm used.

High-Volume Testing and DC Offset Trimming Technique of On-Die Bandgap Voltage Reference for SOCs and Microprocessors

Since the VLSI chips were invented, as predicted by Moore’s law, the performance, the power, and the cost of the VLSI chips have been improved, which brought a significant benefit to the economy. However, some of the analog circuits do not get a full benefit from the scaling, due to the increased device variability with transistors in smaller dimension. Under such circumstance, the calibration and trimming techniques are essential to overcome the sensitivity to the process variation. This paper presents the trimming technique to correct the direct current (dc) offset error of the bandgap voltage reference circuit, which complies with the high-volume manufacturing (HVM) requirements. The proposed trimming method consists of the combination of two different sequences, the coarse and fine trimming. The accuracy of the dc offset trimming is evaluated by the newly invented method that complies with the HVM requirements. With a compact silicon area of only 700 $\mu \text{m}^{2}$ , the dc offset trimming circuit achieved an accuracy of ±5 mV ( $4\sigma$ ) as a result of the coarse and fine trimming operations.

Heterogeneously Integrated InP\/Silicon Photonics: Fabricating Fully Functional Transceivers

Silicon (Si) photonics research and development started more than 30 years ago and has intensified in the last 15 years as levels of device functionality, photonic integration, and commercialization have all increased [1]. The key drivers for using Si in photonics arise from the quality of wafers and the superior processing capabilities developed and funded by the microelectronics industry. It has the promise to revolutionize the photonics industry in the same way that CMOS design and processing revolutionized the microelectronics industry, by driving down photonic chip cost while enabling higher levels of photonic integration and functionality. Commercialization, so far, has focused on optical communication (Telecom [2] and data center [3]) and biosensing [4], with a wealth of future application areas, including high-performance computing [5], automotive (lidar) [6], optical switches [7], and artificial intelligence [8].

Hardware Implementation of Energy Efficient Deep Learning Neural Network Based on Nanoscale Flash Computing Array

AbstractDeep learning neural network (DNN) can provide efficient approaches to process the increasing unstructured data, such as images, audio, and video. To improve the computing power and the energy efficiency of data processing in DNN, a universal and reconfigurable computing paradigm with the hardware implementation scheme including the convolution, pooling, and fully connected layers is developed based on nanoscale flash computing arrays, which can be massively fabricated. Via precisely tuning the threshold voltage, the fabricated 65 nm nanoscale flash cells can exhibit 16 levels (four bits) of storage states. To confirm the feasibility of the computing paradigm, an exemplary five‐layer DNN is simulated based on the measured data from the nor‐type (NOR) flash memory and exhibits 97.8% recognition accuracy of Modified National Institute of Standards and Technology (MNIST) handwritten digit database with the speed of 4.2 × 105 fps at 104 MHz operating frequency. The proposed paradigm with low energy and chip cost shows great promise for future energy efficient and massively parallel data processing of DNN.

Determining the repair and maintenance cost of wood chippers

Chipping weighs heavily on the total delivered cost of wood fuel, which calls for accurate chipping cost estimates. Chipper repair and maintenance cost is perhaps the most obscure among the figures required for a reliable estimate of chipping cost. To clarify this issue, the authors examined the long-term repair and maintenance records for 51 wood chippers operated by 48 chipping service contractors. Repair and maintenance represented between 1.5% and 29% of total chipping cost, inclusive of fuel and labour (mean = 14%). The ratio between total accumulated repair (TAR) cost and machine price averaged 32% and varied with total use. The relationship between total use and TAR to price ratio was explored through regression analysis, which produced a very strong model (R2 = 0.8). This model predicts a TAR to price ratio of 0.64 at 10000 h, with no significant differences between tractor-driven and independent-engine machines. While the coefficients are different, the structure of this model offers a good match with the repair and maintenance cost models developed for farm tractors and other agricultural machinery. A second model was developed for estimating repair and maintenance cost as a function of fuel consumption. The study also provides reference figures for the contribution of labour cost to total maintenance cost. Farm tractors incur more repairs than preventive maintenance, contrary to the other dedicated components of the chipping operation, where preventive maintenance represents most of maintenance cost. Forestry users should make allowance for the lower structural strength of tractors and select large models.

Allocation of Mobile Chippers for a Concentrated Bioenergy Demand

Allocation of mobile chippers is a tactical problem of management in a bioenergy supply chain. It influences the entire supply cost of the wood chip since the transportation distance and the chipping productivity decide the transportation cost. Great and concentrated demands of woody biomass require multiple suppliers, and there should be the best allocation of mobile chippers which minimize the entire supply cost. This study aims to clarify better management of the supply chain consisting of multiple players for a great and concentrated demand for wood chip. The model was a supply chain for a typical biomass power plant with 5.8 MW capacity. Suppliers were assumed to select mobile chippers from two sizes, 140-kW and 353-kW. By the model simulation, it was clarified that the well-considered allocation of two different mobile chippers could reduce the entire supply cost less than the conventional system using a fixed chipper at the power plant. The best management was to use only the 353-kW chippers, and secondly to allocate the less productive chippers closer to the demand to prevent the incline of the transportation cost. However, the possible conflict was also specified as the increased cost of the suppliers using more productive chippers in the second best allocation strategy. This result emphasizes the necessity of resolving such conflict by making the collaborative relationship among stakeholders which has been pointed out by other researches as well to sustain the better condition of the supply chain.

Battery-Less NFC Sensor for pH Monitoring

In this paper, we present a low-cost battery-less color sensor based on Near Field Communication (NFC). This system consists of a color sensor connected to a low-power microcontroller connected to an NFC chip. The energy needed to power up the chipset is retrieved from the magnetic field generated by the reader, i.e., a commercial smartphone. The low cost of NFC chips affords the opportunity to manufacture low-cost tags with sensing capability. We have developed a mobile application to simultaneously present the data and send them to a database in the cloud. The system has been tested with several pH reactive strips. The pH was determined via color measurement using the HSV color space. A simple linear relationship was found between the Hue parameter and the pH. Comparison with the pH determination via smartphone camera showed that the accuracy was greater when the NFC colorimeter was used.

Mm‐wave power control

mm‐wave power control

Short-Circuit Robustness of SiC Trench MOSFETs

An investigation into the robustness of 1200-V/80-mΩ commercial trench-gate MOSFETs reveals that the critical energy for failure during short-circuit operation is reached in shorter times in comparison to similarly rated planar DMOSFETs under similar stress conditions. This critical energy for trench devices was estimated to be between 615 mJ to 660 mJ depending on the gate-drive voltage. These values are considerably smaller when compared to DMOSFETs from the same manufacturer. In comparison to planar designs, trench devices can have lower losses, and manufactured with much smaller chip size for the same device rating. As a result, higher power density, improved efficiency, lower chip costs, and higher yields for trench designs are possible, but these enhancements are offset by a reduction in short-circuit capability. The critical short-circuit time for a 600-V bus voltage is shown to be dependent on gate-drive voltage magnitude, with higher gate voltages leading to increased peak short-circuit current, higher power dissipation, and reduced short-circuit capability.

Microchips track organ mimics

Organoids—tiny spherelike tissues that mimic human organs—can be used to test drugs to predict responses in patients, because they imitate organs’ multicellular complexity and three-dimensional structure better than cell lines. Tracking organoids’ origins is important during testing, but tagging techniques for tracking can be labor intensive and costly. Now, Takanori Takebe and colleagues at Cincinnati Children’s Hospital Medical Center have integrated radio frequency (RF) chips into liver organoids, allowing wireless identification (iScience 2018, DOI: 10.1016/j.isci.2018.05.007). Each chip costs only about 10–20 cents, and they reduce total screening time from months to days. The biologists made organoids from pluripotent stem cells from 10 different human donors, some healthy and some with a liver disease. At an early stage of organoid formation, they placed an RF chip, which eventually sits within the cavity of the resulting sphere, onto the cells. These chip-embedded liver organoids don’t differ from...

Route to one-step microstructure mold fabrication for PDMS microfluidic chip

The microstructure mold fabrication for PDMS microfluidic chip remains complex and time-consuming process requiring special equipment and protocols: photolithography and etching. Thus, a rapid and cost-effective method is highly needed. Comparing with the traditional microfluidic chip fabricating process based on the micro-electromechanical system (MEMS), this method is simple and easy to implement, and the whole fabrication process only requires 1-2 h. Different size of microstructure from 100 to 1000 μm was fabricated, and used to culture four kinds of breast cancer cell lines. Cell viability and morphology was assessed when they were cultured in the micro straight channels, micro square holes and the bonding PDMS-glass microfluidic chip. The experimental results indicate that the microfluidic chip is good and meet the experimental requirements. This method can greatly reduce the process time and cost of the microfluidic chip, and provide a simple and effective way for the structure design and in the field of biological microfabrications and microfluidic chips.

Compensator-Free Mixed-Ripple Adaptive On-Time Controlled Boost Converter

A mixed-ripple adaptive on-time controlled boost converter is proposed. With the proposed control method, the compensator network is no longer required. Hence, the chip area and cost can be reduced, and a satisfied load regulation still can be achieved. Besides, a novel on-time generator is proposed to fix the switching frequency in continuous conduction mode (CCM). Moreover, a differential difference comparator is proposed to simplify the circuits and further reduce chip area. Furthermore, with the proposed control, the converter is capable of smoothly switching between discontinuous conduction mode and CCM, depending on the loading condition. The proposed boost converter was implemented by using a 0.18- $\mu \text{m}$ 1P6M mixed-signal process, and the chip area is 0.88 mm2. The input voltage may range from 0.8 to 1.4 V, the output voltage is set to 1.8 V, and the measured peak efficiency is 92.4%.

High-Efficiency Revolving-Turret Chip Transferring Technology for Flip Chip Packaging

With the rapid growth of the microelectronic packaging market, it is necessary to increase the throughput and reduce the cost of flip chip. Driven by these evolutions, a novel revolving-turret chip transferring (RTCT) technology is introduced to implement high-throughput flip chip packaging. The unnecessary time delays of packaging processes could be eliminated in the RTCT technology due to its parallel manner of motions. In order to analyze the packaging efficiency, the layout and movement sequence of the packaging system are studied, and a calculation model of packaging efficiency is proposed. Furthermore, the effects of the critical parameters (the horizontal and the vertical spacing of antennas and the maximum velocity and acceleration of the turret-type head) on packaging efficiency are investigated to search out the optimal parameters combination. To verify the performance of the RTCT technology under optimal parameters combination, two cases are implemented and compared. The results show that due to parallel motions of processes, unnecessary delays affecting the packaging efficiency have been reduced, and the packaging efficiency of ALN-9714 inlay could be more than 35k chips per hour. In addition, compared with the conventional flip chip packaging process, the RTCT technology is more effective in packaging the chips on antennas with multicolumn layout and small horizontal spacing.

Disposable silicon-glass microfluidic devices: precise, robust and cheap.

Si-glass microfluidics have long provided unprecedented precision, robustness and optical clarity. However, chip fabrication is costly (∼500 USD per chip) and in practice, devices are not heavily reused. We present a method to reduce the cost-per-chip by two orders of magnitude (∼5 USD per chip), rendering Si-glass microfluidics disposable for many applications. The strategy is based on reducing the area of the chip and a whole-chip manifolding strategy that achieves reliable high-pressure high-temperature fluid connectivity. The resulting system was validated at 130 bar and 95 °C and demonstrated in both energy and carbon capture applications. We studied heavy oil flooding with brine, polymer, and surfactant polymer solutions and found the surfactant polymer as the most effective solution which recovered ∼80% of the oil with the least amount of injection while maintaining a relatively uniform displacement front. In a carbon capture application, we measured the dilation of an emerging ionic liquid analog, choline chloride with urea, in gaseous and supercritical CO2. Previously restricted to niche microfluidic applications, the approach here brings the established benefits of Si-glass microfluidics to a broad range of applications.

A 41.3/26.7 pJ per Neuron Weight RBM Processor Supporting On-Chip Learning/Inference for IoT Applications

An energy-efficient restricted Boltzmann machine (RBM) processor (RBM-P) supporting on-chip learning and inference is proposed for machine learning and Internet of Things (IoT) applications in this paper. To train a neural network (NN) model, the RBM structure is applied to supervised and unsupervised learning, and a multi-layer NN can be constructed and initialized by stacking multiple RBMs. Featuring NN model reduction for external memory bandwidth saving, low power neuron binarizer (LPNB) with dynamic clock gating and area-efficient NN-like activation function calculators for power reduction, user-defined connection map (UDCM) for both computation time and bandwidth saving, and early stopping (ES) mechanism for learning process, the proposed system integrates 32 RBM cores with maximal 4k neurons per layer and 128 candidates per sample for machine learning applications. Implemented in 65nm CMOS technology, the proposed RBM-P chip costs 2.2 M gates and 128 kB SRAM with 8.8 mm2 area. Operated at 1.2 V and 210 MHz, this chip achieves 7.53G neuron weights (NWs) and 11.63G NWs per second with 41.3 and 26.7 pJ per NW for learning and inference, respectively.

Economic efficiency of willow, poplar and black locust production using different soil amendments

Profitability of biomass production is the main condition to be fulfilled for farmers to be more interested in growing short rotation woody crops (SRWC). The aim of this study was to assess the cost and economic efficiency of production of chips from three SRWC species (willow, poplar, black locust) depending on the soil amendment method, biomass prices and the transportation distance to the end user. The economic analysis assessed the cost of dry chips and unit energy production, revenue, discounted pay-back period, net present value and internal rate of return.In the base scenario the highest revenue 292 € ha−1 year−1 was found for willow amended with lignin. The best revenue for poplar (194 € ha−1 year−1) was achieved when the crop was fertilised with mineral fertiliser and amended with lignin. No options for black locust were profitable. Other economic indices were the best in the production of willow as well. The change in the biomass price and transport distance influenced the revenue in the production of all species. Our study has indicated the importance of the right choice of species and method of soil amendment, as this determined the biomass yield and it had a great effect on the cost of chip production and the amount of revenue gained from such production.

Selection of chipper engine size based on business scale and optimised cost of chipping and transportation

ABSTRACTThe best chipper engine size was obtained by optimising the chipping operation according to business scale and transportation cost. The total chip supply cost could be reduced by improving the rate of machine utilisation of chippers. From regression analysis, the engine power of chippers expressed well the chipping and transportation costs, and the trade-off relationship between these costs was proved by the model supply chain in Iwate Prefecture, Japan. The chipper with a middle-sized engine, with an engine power of 200–400 kW, was the best choice in the perspective of economy and transportation management while the business scale needed to be at least 20,000 solid m3 year−1. The total supply cost by a chipper with a smaller engine was not the best but it could be recommended to attract small-scale companies that produce less than 10,000 solid m3 year−1. Chippers with a larger engine could be introduced if the business scale was about 50,000 solid m3 year−1. However, even if the chipping cost could be reduced, the supply chain would require larger trucks or trailers on such a large business scale. The shuttle transportation system needs to be improved to reduce the unloading time that occupies one-fifth to one-fourth of a cycle time and empty drives.

PENINGKATAN DAYA SAING MELALUI PERBAIKAN PERHITUNGAN HARGA POKOK PRODUKSI INDUSTRI KERIPIK DAN SEJENISNYA

Dedication held at Jl. Gaperta, Village Central Helvetia, district of Medan Helvetia, Medan, North Sumatra. Dedication took the title "Increasing Sales Through Improved Calculation of Cost of Production Industry Chips and Peyek". Community service will be made to the two businessmen households of preliminary surveys noting that the two housewives who do it faces constraints in which the products can not be marketed in the modern market or supermarkets because they do not have permission from the Ministry of Health (PIRT) and yet have the certificate Halal and requires few tools left to run the business that has been running for about four years and the effort the other household else has run the business for longer than the others which is about nine years had several employees freelance help in producing products that already have a name of "Kartika" which already has a permit Din Kes port on 215127501152 and already has a certificate from the Halal MUI no; 090100891110 has six types of products namely: cheese potato chips, cheese potato chips, carrot chips cheese, peanut dent, dent dent anchovies and spinach, facing obstacles unavailability of machines to grind boiled carrots and tools to attenuate the dough in bulk for processing production. Service to the community team will strive to help business partners for the constraints that it faces so as to produce a better business. Goal mono community service activities this year is expected to develop a business venture partner that had only done penjulan in traditional markets and by booking with a permit from the Department of Health and halal certificate from MUI venture partner product can be sold in modern markets or in supermarkets and mall- mall that is around the city of Medan and in turn will expand to other cities in North Sumatra

Fabrication and characteristics of excellent current spreading GaN-based LED by using transparent electrode-insulator-semiconductor structure**Project supported by the Natural Science Foundation of China (Nos. 61306051, 61306050) and the National High Technology Program of China (No. 2014AA032606).

GaN-based vertical light-emitting-diodes (V-LEDs) with an improved current injection pattern were fabricated and a novel current injection pattern of LEDs which consists of electrode-insulator-semiconductor (EIS) structure was proposed. The EIS structure was achieved by an insulator layer (20-nm Ta2O5) deposited between the p-GaN and the ITO layer. This kind of EIS structure works through a defect-assisted tunneling mechanism to realize current injection and obtains a uniform current distribution on the chip surface, thus greatly improving the current spreading ability of LEDs. The appearance of this novel current injection pattern of V-LEDs will subvert the impression of the conventional LEDs structure, including simplifying the chip manufacture technology and reducing the chip cost. Under a current density of 2, 5, 10, and 25 A/cm2, the luminous uniformity was better than conventional structure LEDs. The standard deviation of power density distribution in light distribution was 0.028, which was much smaller than that of conventional structure LEDs and illustrated a huge advantage on the current spreading ability of EIS-LEDs.

Design of a high precision digital interface circuit for capacitive MEMS accelerometers with floating point ADC

Traditional analog blocks such as integrators are widely used in high precision MEMS accelerometers. However there is few cost-effective method to address the problem of analog integrators’ output saturation due to the integrators’ input offsets. A high precision digital capacitive MEMS accelerometer interface based on the traditional capacitive MEMS accelerometer sigma-delta interface is proposed to address this issue. An instantaneous floating point analog-to-digital converter (IFP ADC) is proposed to convert the analog frond-end amplifier (AFE) output signal to digital signal. The IFP ADC is very effective to digitalize the signal of the proposed interface circuit output, which is similar to Gaussian distribution. A Matlab simulation model is developed to evaluate the theory model. The implementation of digital loop filter realized in a FPGA board can overcome integrator offset issue. In addition, it is much easier to optimize a digital loop filter's parameter and reduce the chip cost. In this work, the AFE and voltage reference etc. are successfully fabricated by using the 0.18µm mixed-signal CMOS process. The sensitivity and the noise floor of the AFE are respectively 0.71V/pF and 3.16µV/rt(Hz) in an open loop measurement. The evaluation PCB experimental result shows that the noise floor of the system is −135dBg/rt(Hz).