Chip Carrier Package Research Articles

Low Loss/Low CTE Semiconductor Carrier Packaging Thin Core Material

There is an ever-increasing need by semiconductor/packaging companies for the introduction of a low loss, ultra-low Coefficient of Thermal Expansion chip carrier packaging substrate core material that provides a cost-effective method for producing thin core build up with very dense core vias. This low loss, low CTE flip-chip substrate core is well suited to multi-layer, RF, and applications requiring a system-in-package approach. This paper discusses a novel substrate core material using a build-up film dielectric layer in conjunction with glass fiber weave. Key properties include low loss (Df<0.002), a CTE from 5 - 10 ppm/C, extremely high thermal reliability, and low modulus. An advantage of using glass fiber weave instead of Invar, for instance, is the extremely low CTE that can be achieved while still maintaining a non-conductive power or ground plane. Multilayer circuits using PTFE can suffer from extremely high lamination temperatures, high cost, and low overall yields due to the inability of the soft material to go through a desmear process. Substrate core materials have the primary benefit that they offer stability and increased reliability of many subsequent build-up microvia layers. As monolithic semiconductors are replaced by chiplets, there is a growing need to package many types of chiplets without losing the signal integrity performance of a monolithic semiconductor on a single IC package. An extremely low loss substrate core offers the potential benefit that unique chiplet packaging architectures can be designed with the lowest possible dielectric losses due to the multichip interconnect strategy.

Analysis of the Thermally Induced Packaging Effects on the Frequency Drift of Micro-Electromechanical System Resonant Accelerometer.

Due to the working principle of MEMS resonant accelerometers, their thermally induced frequency drift is an inevitable practical issue for their extensive application. This paper is focused on reducing the thermally induced packaging effects on the frequency drift. A leadless ceramic chip carrier package with a stress-buffering layer was proposed for a MEMS resonant accelerometer, and the influences of packaging structure parameters on the frequency drift were investigated through finite element simulations and verified experimentally. Because of the thermal mismatch between dissimilar materials, the thermo-mechanical stress within the resonant beam leads to a change in the effective stiffness and causes the frequency drift to decrease linearly with increasing temperature. Furthermore, our investigations reveal that increasing the stress-buffering layer thickness and reducing the solder layer thickness can significantly minimize the thermo-mechanical stress within the resonant beam. As the neutral plane approaches the horizontal symmetry plane of the resonant beam when optimizing the packaging structure, the effects of the compressive and tensile stresses on the effective stiffness of the resonant beam will cancel each other out, which can dramatically reduce the frequency drift. These findings provide guidelines for packaging design through which to improve the temperature stability of MEMS resonant accelerometers.

Bias-Repeatability Analysis of Vacuum-Packaged 3-Axis MEMS Gyroscope Using Oven-Controlled System.

The performance of microelectromechanical system (MEMS) inertial measurement units (IMUs) is susceptible to many environmental factors. Among different factors, temperature is one of the most challenging issues. This report reveals the bias stability analysis of an ovenized MEMS gyroscope. A micro-heater and a control system exploiting PID/PWM were used to compensate for the bias stability variations of a commercial MEMS IMU from BOSCH "BMI 088". A micro-heater made of gold (Au) thin film is integrated with the commercial MEMS IMU chip. A custom-designed micro-machined glass platform thermally isolates the MEMS IMU from the ambient environment and is vacuum sealed in the leadless chip carrier (LCC) package. The BMI 088 built-in temperature sensor is used for temperature sensing of the device and the locally integrated heater. The experimental results reveal that the bias repeatability of the devices has been improved significantly to achieve the target specifications, making the commercial devices suitable for navigation. Furthermore, the effect of vacuum-packaged and non-vacuum-packaged devices was compared. It was found that the bias repeatability of vacuum-packaged devices was improved by more than 60%.

An Ultrahigh Vacuum Packaging Process Demonstrating Over 2 Million Q-Factor in MEMS Vibratory Gyroscopes

Micro resonators and vibratory gyroscopes could reach their fundamental thermo-elastic damping (TED) limit in an ultravacuum condition where the viscous damping is eliminated. This article presents a reliable and repeatable high vacuum sealing process as a standalone approach for performance evaluation of dynamic micro devices. We demonstrated a micro-Torr vacuum level in a ceramic leadless chip carrier package and achieved the Q-factor over 2million on a quad mass gyroscope, approaching the TED limit of the device by effectively eliminating the viscous damping. The long-term vacuum stability was characterized over 1 year and demonstrated that the Q-factor does not degrade over time and even continues improving. The long-term ultrahigh vacuum condition is enabled by surface desorption prior to sealing, pumping of residual gases by passive getters, and defect-free solder reflow in the sealing area. The experimental results confirmed the reliability and repeatability of the proposed sealing procedure, which can be adapted for other Micro Electro-Mechanical Systems (MEMS) with ultrahigh vacuum requirements.

A 2.5-D Integrated Data Logger for Measuring Extreme Accelerations

A very compact and rugged 2.5-D integrated data logger has been built and tested. The data logger is capable of measuring accelerations exceeding 70 000 g. Microcontroller and flash memory as bare dies have been mounted onto a silicon interposer with through silicon vias using anisotropic conductive film and Au stud bump bonding. A microelectromechanical system accelerometer is mounted onto the interposer, using a robust customized flip-chip mounting approach. The interposer is mounted into a 16-pin leadless chip carrier package using isotropic conductive adhesive, where the conductive part is made of metallized polymer spheres. The ceramic package was mounted onto an application printed circuit board (PCB) with filters, power management, and an interface contact, using soldered plastic core solder balls (PCSBs). The diameter of the data logger is less than 9 mm, and the height is approximately 5 mm. The data logger fits within 12.7-mm (0.50 cal.) projectile, and acceleration measurements have been performed during firing, flight, and recovery. The measured accelerations have been verified by comparing the calculated projectile muzzle velocities with Doppler radar measurements.

Whisker Formation on SAC305 Soldered Assemblies

This article describes the results of a whisker formation study on SAC305 assemblies, evaluating the effects of lead-frame materials and cleanliness in different environments: low-stress simulated power cycling (50–85°C thermal cycling), thermal shock (–55°C to 85°C), and high temperature/high humidity (85°C/85% RH). Cleaned and contaminated small outline transistors, large leaded quad flat packs (QFP), plastic leaded chip carrier packages, and solder balls with and without rare earth elements (REE) were soldered to custom designed test boards with Sn3Ag0.5Cu (SAC305) solder. After assembly, all the boards were cleaned, and half of them were recontaminated (1.56 µg/cm2 Cl−). Whisker length, diameter, and density were measured. Detailed metallurgical analysis on components before assembly and on solder joints before and after testing was performed. It was found that whiskers grow from solder joint fillets, where the thickness is less than 25 µm, unless REE was present. The influence of lead-frame and solder ball material, microstructure, cleanliness, and environment on whisker characteristics is discussed. This article provides detailed metallurgical observations and select whisker length data obtained during this multiyear testing program.

Focus on sensors and detectors

Focus on sensors and detectors

Thermo-Mechanical Reliability Evaluation of PLCC Packaging

Thermo-mechanical failure is the main factor to impact the microelectronic packaging reliability. Under thermal loads, the microelectronic packaging is easy to produce cracks, delamination, voids, and other defects, which can emerge and grow under thermo-mechanical stresse caused by the different coefficients of thermal expansion (CTE). Firstly, a geometric model of Plastic Leaded Chip Carrier (PLCC) packaging was established and the thermo-mechanical property of PLCC packaging was analyzed using finite element analysis (FEA) software ANSYS. Then, the thermal cycling test on a set of PLCC packaging was conducted according to the MIL-STD-883H Microcircuits Test Method Standard with temperature range from-65°C to 150°C, and the crack growth rate of PLCC packaging was studied experimentally using Scanning Acoustic Microscopy (SAM). Finally, the Anand model was adopted to predict thermal fatigue life, which was consistent with the experimental results. With these researches, the thermo-mechanical reliability evaluation of the PLCC packaging was investigated using finite element analysis (FEA) combined with analytical methods.

Numerical Investigation of Heat Transfer of Twelve Plastic Leaded Chip Carrier (PLCC) by Using Computational Fluid Dynamic, FLUENT<sup>TM</sup> Software

Plastic Leaded Chip Carrier (PLCC) package has been emerged a promising option to tackle the thermal management issue of micro-electronic devices. In the present study, three dimensional numerical analysis of heat and fluid flow through PLCC packages oriented in-line and mounted horizontally on a printed circuit board, is carried out using a commercial CFD code, FLUENTTM. The simulation is performed for 12 PLCC under different inlet velocities and chip powers. The contours of average junction temperatures are obtained for each package under different conditions. It is observed that the junction temperature of the packages decreases with increase in inlet velocity and increases with chip power. Moreover, the increase in package density significantly contributed to rise in temperature of chips. Thus the present simulation demonstrates that the chip density (the number of packages mounted on a given area), chip power and the coolant inlet velocity are strongly interconnected; hence their appropriate choice would be crucial.

The Comparison between Four PLCC Packages and Eight PLCC Packages in Personal Computer (PC) Using Computational Fluid Dynamic (CFD), FLUENT Software<sup>TM</sup> Using Epoxy Moulding Compound Material (EMC)

The paper present the three dimensional numerical analysis of heat and fluid flow through Plastic Leaded Chip Carrier (PLCC) packages in inline orientation horizontally mounted on a printed circuit board in a wind tunnel is carried out using a commercial CFD code, FLUENTTMby using Epoxy Moulding Compound (EMC) as a main material. The study was made for four and eight packages with different Reynolds Number and package chip powers. The results are presented in term of junction temperature for four and eight PLCC package under different conditions. It is observed the chip temperatures of eight PLCC packages have higher junction temperature compare to four PLCC packages due to effect of other PLCC because of space and gap between PLCC that have more number of PLCC is smaller. Hence it makes junction temperature of eight PLCC higher compare to four PLCC packages. Moreover, the junction temperature of the packages decreases with increase in Reynolds Number.

Study on MEMS board-level package reliability under high-G impact

Under high-G (104 g or above) impact load conditions, the reliability of micro electro mechanical systems (MEMS) board-level package and interconnection are critical concerned that influence the mission success of total projectile. This paper conducts a research on this problem to analyze package reliability using finite element modelling (FEM) and simulation method. Theoretical analysis and mathematical model for failure mechanism of MEMS package under high-G impact are conducted and established. A FEM dynamic analysis is conducted on a typical MEMS board-level leadless chip carrier (LCC) package. Results show that the solder joints are one of the key weakness points that influence the reliability of MEMS package. The maximum effective stress in the structure occurs at the outer corner in the outermost solder point, and the alloy cover and printed circuit board (PCB) have a greater deformation.

Hermetic glass frit packaging in air and vacuum with localized laser joining

Glass frit packaging is a simple and robust method used for hermetic sealing of micro-devices. Conventional glass frit packaging processes rely on furnace heating where the entire package is heated to elevated temperatures, hence restricting the use of temperature-sensitive materials inside the package and generating problems in multi-stage packaging processes. The use of a laser as an alternative heat source offers the possibility of highly localized heating where the heat-input can be restricted to the joining area only. In this paper the clear benefits of combining glass frit packaging and localized laser heating are demonstrated. Two novel laser-based glass frit packaging processes for sealing of leadless chip carrier (LCC) packages in both air and vacuum have been developed. Full hermetic seals according to MIL-STD-883G are achieved in high yield processes where the temperature in the centre of the device is kept at least 230 °C below the temperature in the joining region.

Numerical investigation of heat transfer in Plastic Leaded Chip Carrier (PLCC) packages in in-line arrangement

Plastic Leaded Chip Carrier (PLCC) package has been emerged a promising option to tackle the thermal management issue of micro-electronic devices. In the present study, three dimensional numerical analysis of heat and fluid flow through PLCC packages oriented in-line and mounted horizontally on a printed circuit board, is carried out using a commercial CFD code, FLUENTTM. The simulation is performed for three configurations such as 4PLCC, 8PLCC and 12PLCC under natural, mixed and forced convection modes with different inlet velocities and chip powers. The contours of average junction temperatures are obtained for each package under different conditions. It is observed that the junction temperature of the packages decreases with increase in inlet velocity and increases with chip power. Moreover, the increase in package density significantly contributed to rise in temperature of chips. Thus the present simulation demonstrates that the chip density (the number of packages mounted on a given area), chip power and the coolant inlet velocity are strongly interconnected; hence their appropriate choice would be crucial. Keywords: PLCC package, Thermal management, Numerical simulation, Average junction temperature

Packaging Effects on RadFET Sensors for High Energy Physics Experiments

RadFETs in customized chip carrier packages are installed in the LHC Experiments as radiation monitors. The package influence on the dose measurement in the complex LHC radiation environment is evaluated using Geant4 simulations and experimental data.

3-D conjugate heat transfer analysis of PLCC packages mounted in-line on a Printed Circuit Board

This paper presents a three dimensional heat and fluid flow analysis of two Plastic Leaded Chip Carrier (PLCC) packages mounted in tandem arrangement on a Printed Circuit Board (PCB) exposed to the free stream velocity. The numerical simulation was done using FLUENT 6.3 and the experiments were performed by using an air chamber with nozzle, at different approach air velocities to emulate the forced convection heat transfer phenomena. Parameters such as junction temperature, thermal resistance and top surface average Nusselt number have been studied for each package by varying the chip power, spacing between the packages and approach air velocities. The decrease in the junction temperature of the packages with the increase in approach air velocity is clearly observed. Furthermore, the Nusselt number of PLCC 1 is always slightly higher than PLCC 2 for all approach velocities considered. The results also show that the spacing between packages influences the thermal resistance and average Nusselt number for both packages at a particular approach air velocity. The simulation results obtained are found in satisfactory agreement with the experimental results.

A Low Power Fully CMOS Integrated RF Transceiver IC for Wireless Sensor Networks

A fully CMOS integrated RF transceiver for ubiquitous sensor networks in sub-gigahertz industrial, scientific, and medical (ISM)-band applications is implemented and measured. The integrated circuit is fabricated in 0.18-mum CMOS technology and packaged in leadless plastic chip carrier (LPCC) package. The fully monolithic transceiver consists of a receiver, a transmitter, and an RF synthesizer with on-chip voltage-controlled oscillator. The chip fully complies with the IEEE 802.15.4 wireless personal area network in sub-gigahertz mode. The cascaded noise figure of the overall receiver is 9.5 dB and the overall transmitter achieves less than 6.3% error vector magnitude for 40 kb/s mode. The chip uses 1.8-V power supply and the power consumption is 25 mW for reception mode and 29 mW for transmission mode

Submodeling Analysis for Path-Dependent Thermomechanical Problems

In a finite element analysis, when localized behavior of a large model is of particular concern, generally one would refine the mesh until it captures the local solution adequately. Submodeling is an alternative way for solving this kind of problem. It provides a relatively accurate solution at a modest computational cost. For a valid submodeling analysis, the boundaries of the submodel should be sufficiently far away from local features so that St. Venant’s principle holds. Moreover, special treatments are required for solving problems that involve path-dependent characteristics. This paper presents a general procedure to perform submodeling analyses for path-dependent thermomechanical problems without a priori assumptions on the structural response. The procedure was benchmarked using a bimaterial strip and demonstrated through analyses on a bump chip carrier package assembly. The procedure is conducive to the numerical assessment of fatigue lives of electronic packages.

A Performance and Manufacturability Evaluation of Bump Chip Carrier Packages

Bump chip carrier [(BCC) registered trademark of Fujitsu Ltd.] is an attractive solution to the demand of high packaging density of low input/output (I/O)-count packages. In this paper, an extensive finite element thermomechanical analysis has been conducted to evaluate the reliability of BCC packages, both with and without heat slugs, during thermal cycling. The effect of a variety of parameters on package reliability has been evaluated, including board thickness, package size mold material, solder paste thickness, and terminal height. The solder reliability of corner leads versus inner leads, as well as square leads versus rectangular leads has also been investigated. During manufacturing, molded panels for BCC packages undergo significant warpage. Two types of mold designs are compared through three-dimensional finite element analysis. A variety of mold compound materials have been evaluated. The most effective ways to reduce manufacturing-induced warpage have been suggested.

Localized, In-Situ Vacuum Measurements For MEMS Packaging

ABSTRACTMEMS devices have unique packaging considerations compared to conventional semiconductor devices. They tend to have relatively large die size and many architectures cannot tolerate elevated temperatures. Often these devices require a vacuum environment for efficient operation. While advances have been made in hermetic packaging of MEMS devices, vacuum packaging remains elusive. One significant problem in developing vacuum sealing has been the inability to determine, readily and non-destructively, the vacuum level inside the package. We have previously described the development of a silicon MEMS-based chip design, “SensorChip™,” with integrated photonic crystal and reflective optics, which uses narrow-band optical emission and absorption for selective identification of gas and chemical species. Because the power consumption required to maintain a specific temperature is directly related to the vacuum level, these devices effectively serve as microscopic Pirani gauges – local vacuum sensors in the moderate vacuum range (0.01 to 1.0 torr) of interest to MEMS devices. Using the membrane itself as a vacuum gauge during sealing has proven to be an invaluable tool in developing a robust vacuum seal in a leadless chip carrier package. It has enabled us to optimize choice of design, materials and processing.

Electrical performance improvements on RFICs using bump chip carrier packages as compared to standard thin shrink small outline packages

The electrical models of bump chip carrier (BCC) packages have been established based on the S-parameter measurement. When compared to the standard thin shrink small outline packages (TSSOPs), BCC packages show much smaller parasitics in the equivalent model. In the simulation, the insertion and return losses for a packaged 50-/spl Omega/ microstrip line are calculated against frequency. BCC packages are also less lossy than TSSOPs over a wide frequency range. By setting a random variable with Gaussian distribution varied within a certain range for each equivalent circuit element of the packages, the Monte Carlo analysis has been performed to study the package effects on a GaAs heterojunction bipolar transistor (HBT). Again, BCC packages cause less decrement of HBT unity-gain bandwidth than TSSOPs.