Charged Device Model Electrostatic Discharge Research Articles

Investigation of CDM ESD Protection Capability Among Power-Rail ESD Clamp Circuits in CMOS ICs With Decoupling Capacitors

The power-rail electrostatic discharge (ESD) clamp circuits have been widely used in CMOS integrated circuits (ICs) to provide effective discharging paths for on-chip ESD protection design. Among all ESD events, the most serious threat is posed to ICs by the charged-device model (CDM), as compared with other ESD models. In this work, the CDM ESD protection capability among different power-rail ESD clamp circuits was studied and analyzed with the very-fast transmission line pulse (VF-TLP) and all the measurements are performed at room temperature. The combinations of power-rail ESD clamp circuits with internal circuits together, which are realized by ring oscillator and different decoupling capacitors, were fabricated in the 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS technology with the 1.8-V devices to further investigate their overall CDM ESD robustness under chip-level field-induced CDM (FI-CDM) ESD stress. The investigation result of this work is helpful to provide the best selection on the power-rail ESD clamp circuit for on-chip CDM protection design in CMOS ICs.

Stacking-MOS Protection Design for Interface Circuits Against Cross-Domain CDM ESD Stresses

Electrostatic discharge (ESD) is still a challenging reliability issue for integrated circuits (ICs) in advanced CMOS technology. With the development of ICs toward system-on-chip (SoC) applications, it has been common to integrate multiple separated power domains into a single chip for power management or noise isolation considerations. Besides, the fabricated transistors with thinner gate oxide for high-speed operation cause the ICs more sensitive to charged-device model (CDM) ESD events, especially under cross-domain stresses. The traditional cross-domain CDM ESD protection would result in some restrictions on circuit applications or cause some performance degradation. Thus, a new protection design with stacking footer/header metal-oxide-semiconductor (MOS) structure against cross-domain CDM ESD stresses was proposed in this work and verified in 0.18-μm CMOS technology. The proposed design got higher ESD robustness under CDM and HBM (human body model) ESD tests. Moreover, the CDM robustness of different stacking-MOS protection designs was also investigated in detail.

Study on CDM ESD Robustness Among On-Chip Decoupling Capacitors in CMOS Integrated Circuits

The integrated circuit (IC) products fabricated in the scaled-down CMOS processes with higher clock rate and lower power supply voltage (VDD) are more sensitive to the transient/switching noises on the power lines with the parasitic inductance induced by the bonding wire. The typical method to suppress the power line noise is to add on-chip decoupling capacitors. Meanwhile, electrostatic discharge (ESD) is also a challenging issue on IC reliability in advanced CMOS technology. For the ICs fabricated in an advanced process, with the thinner gate oxide, the circuits are particularly vulnerable to the charged-device model (CDM) ESD events. However, there was very limited research to investigate the ESD robustness on the decoupling capacitors, especially during the CDM ESD events. In this work, the CDM ESD robustness among different types of decoupling capacitors in ICs was investigated in a 0.18- ${\mu }\text{m}$ CMOS technology.

Non-Pad-Based in Situ In-Operando CDM ESD Protection Using Internally Distributed Network

Charged device model (CDM) electrostatic discharge (ESD) protection is an emerging design challenge to ICs at advanced technology nodes. It was recently reported that the traditional pad-based CDM ESD protection methods are fundamentally faulty, which causes uncertainties in CDM ESD protection designs, testing and failure analysis. Re-thinking of onchip CDM ESD protection becomes imperative for complex ICs implemented in advanced technologies. This paper reports a disruptive CDM ESD protection method utilizing non-pad-based internally-distributed ESD protection network as a robust in situ in-operando CDM ESD protection solution. The proposed internal-distributed CDM ESD protection mesh network can be realized using interposer or through-silicon-via (TSV) ESD protection structures to achieve local 3D CDM ESD protection via heterogeneous integration. The new concept was validated using an internal-CDM-protected oscillator IC implemented in a foundry 45nm silicon-on-insulator (SOI) technology.

Pad-Based CDM ESD Protection Methods Are Faulty

Charged device model (CDM) electrostatic discharge (ESD) protection remains a huge challenge for integrated circuit (IC) reliability designs. The “internal-oriented” CDM model and the “external-oriented” human body model (HBM) describe fundamentally different ESD phenomena. Through the comprehensive analysis, this article concludes that the classic pad-based ESD protection methods, commonly used for “from-external-to-internal” HBM ESD protection, are theoretically not working for “from-internal-to-external” CDM ESD protection. It states that the actual internal distribution of static charges within a chip is vitally critical to CDM ESD protection. The discovery explains the potential root cause of the randomness and uncertainty of pad-based CDM ESD protection designs commonly observed today, hence calls for new CDM ESD protection solutions.

Full-Component Modeling and Simulation of Charged Device Model ESD

This paper presents a methodology to construct an equivalent circuit model of a packaged integrated circuit mounted on a field-induced charged device model electrostatic discharge tester. Circuit simulation is used to obtain the full-component current and voltage distributions. This paper focuses on predicting overvoltage stress at power domain crossing circuits.

Pulsed Hertzian dipole radiation and electrostatic discharge events in manufacturing

A destructive Charged Device Model electrostatic discharge event can happen in semiconductor manufacturing and should be detectable from radiation that results from collapse of an electric dipole. The analytically describable radiation field pulse of CDM can be readily produced with a new instrument that creates dipole collapse at will. A coaxial monopole E-field antenna's transfer function gives the antenna signal in near-field, and experiments compare well with theory. A major feature of the antenna response to this field pulse is a bipolar pulse. A transmission linebased synthetic monocycle pulser, for characterizing antenna-driven ESD detectors, can be built and is described.

Investigation on CDM ESD events at core circuits in a 65-nm CMOS process

Among three chip-level electrostatic discharge (ESD) test standards, which were human-body model (HBM), machine model (MM), and charged-device model (CDM), the CDM ESD events became critical due to the larger and faster discharging currents. Besides input/output (I/O) circuits which were connected to I/O pads, core circuits also suffered from CDM ESD events caused by coupled currents between I/O lines and core lines. In this work, the CDM ESD robustness of the core circuits with and without inserting shielding lines were investigated in a 65-nm CMOS process. Verified in a silicon chip, the CDM ESD robustness of the core circuits with shielding lines were degraded. The failure mechanism of the test circuits was also investigated in this work.

Investigation on Board-Level CDM ESD Issue in IC Products

The impacts caused by board-level charged-device-model (CDM) electrostatic-discharge (ESD) events on integrated-circuit products are investigated in this paper. The mechanism of board-level CDM ESD event is introduced first. Based on this mechanism, an experiment is performed to investigate the board-level CDM ESD current waveforms under different sizes of printed circuit boards (PCBs), charged voltages, and series resistances in the discharging path. Experimental results show that the discharging current strongly depends on the PCB size, charged voltage, and series resistance. Moreover, the chip- and board-level CDM ESD levels of several test devices and test circuits fabricated in CMOS processes are characterized and compared. The test results show that the board-level CDM ESD level of the test circuit is lower than the chip-level CDM ESD level of the test circuit, which demonstrates that the board-level CDM ESD event is more critical than the chip-level CDM ESD event. In addition, failure analysis reveals that the failure in the test circuit under board-level CDM ESD test is much severer than that under chip-level CDM ESD test.

Analysis of charge injection processes including ESD in MEMS

The effect of charge injection due to human body model (HBM) electrostatic discharge (ESD), charged device model (CDM) ESD and triboelectrification in capacitive microelectromechanical systems' (MEMS) structures is analyzed. The results show that as feature size is reduced, the effect remains constant for charging by triboelectrification. However, HBM ESD injected charge produces a change which is inversely proportional to the square of the gap separation and CDM ESD injected charge produces a change which is inversely proportional to the square of the plate area.

Using Coupled Transmission Lines to Generate Impedance-Matched Pulses Resembling Charged Device Model ESD

A quarter-wave directional coupler plus ordinary transmission line pulsing (TLP) can create short pulses resembling charged device model (CDM) electrostatic discharge (ESD). Pulse rise time often relates to the coupler's center frequency and can thereby be stabilized. It is shown that for a voltage step of a given size, yet with arbitrary waveform, the net amount of coupled charge (the charge packet) is constant and depends only on fixed coupler parameters. This property of Z-matched coupled lines has wider implications. High-voltage couplers can be made from coaxial cable or from stripline. Some of these designs are described, tested, and compared to computer simulations of coupled lines

Influence of tester, test method, and device type on CDM ESD testing

In this paper, the charged device model (CDM) electrostatic discharge (ESD) events emulated by different commercial concerns are studied. First, the characteristic waveforms, defined by the EOS/ESD CDM ESD draft standard (DS5.3-1993), are compared and some major problems related to the specification of socketed CDM testers are discussed. Second, the results of an extensive CDM ESD test program are reported. The influences of various test parameters, such as the charging method (direct or field), the discharge mode (contact or noncontact), the charge pin (substrate pin or pin to be discharged) and the device package are studied. Finally, correlations of CDM ESD test results (the voltage thresholds and electrical failure signatures) are investigated. >

Integrated circuit metal in the charged device model: bootstrap heating, melt damage, and scaling laws

Charged-device model electrostatic discharge (CDM ESD) stresses thin metal lines heavily because of strong I 2 R heating, resulting in a wider linewidth requirement as thin AlCu is integrated into multilayer metal systems. Metal heating during a CDM event is shown to strongly depend on device capacitance and on temperature coefficient of resistance.