Charge Trapping Memory Cells Research Articles

Challenges to Optimize Charge Trapping Non-Volatile Flash Memory Cells: A Case Study of HfO2/Al2O3 Nanolaminated Stacks.

The requirements for ever-increasing volumes of data storage have urged intensive studies to find feasible means to satisfy them. In the long run, new device concepts and technologies that overcome the limitations of traditional CMOS-based memory cells will be needed and adopted. In the meantime, there are still innovations within the current CMOS technology, which could be implemented to improve the data storage ability of memory cells-e.g., replacement of the current dominant floating gate non-volatile memory (NVM) by a charge trapping memory. The latter offers better operation characteristics, e.g., improved retention and endurance, lower power consumption, higher program/erase (P/E) speed and allows vertical stacking. This work provides an overview of our systematic studies of charge-trapping memory cells with a HfO2/Al2O3-based charge-trapping layer prepared by atomic layer deposition (ALD). The possibility to tailor density, energy, and spatial distributions of charge storage traps by the introduction of Al in HfO2 is demonstrated. The impact of the charge trapping layer composition, annealing process, material and thickness of tunneling oxide on the memory windows, and retention and endurance characteristics of the structures are considered. Challenges to optimizing the composition and technology of charge-trapping memory cells toward meeting the requirements for high density of trapped charge and reliable storage with a negligible loss of charges in the CTF memory cell are discussed. We also outline the perspectives and opportunities for further research and innovations enabled by charge-trapping HfO2/Al2O3-based stacks.

Transverse dielectric and lateral channel band engineering of drain-side and source-side injection in Ge-based charge-trapping memory cells for energy-efficient applications

Transverse dielectric and lateral channel band engineering of drain-side and source-side injection in Ge-based charge-trapping memory cells for energy-efficient applications

Tunneling oxide engineering for improving retention in nonvolatile charge-trapping memory with TaN/Al2O3/HfO2/SiO2/Al2O3/SiO2/Si structure

In this paper, we demonstrate retention improvement in nonvolatile charge-trapping memory cells by tunneling oxide engineering with Al2O3. By utilizing SiO2/Al2O3/SiO2 layers for the tunneling oxide, it is shown that the threshold voltage window after 10 years is significantly improved from 0.78 V to 4.18 V through Synopsys Sentaurus technology computer-aided design simulation. In addition, retention improvement from incorporating SiO2/Al2O3/SiO2 tunneling layers is compared with that using SiO2/Si3N4/SiO2 tunneling layers. The relationship between charge-trapping layer thickness and trapped charge emission is also investigated. As a result, we open up the possibility of using HfO2 as a charge-trapping layer with significant reliability enhancement.

Total Ionization Dose Effects on Charge Storage Capability of Al2O3/HfO2/Al2O3-Based Charge Trapping Memory Cell**Supported by the National Natural Science Foundation of China under Grant No 616340084, the Youth Innovation Promotion Association of Chinese Academy of Sciences under Grant No 2014101, the International Cooperation Project of Chinese Academy of Sciences, and the Austrian-Chinese Cooperative R&D Projects under Grant No 172511KYSB20150006.

Because of the discrete charge storage mechanism, charge trapping memory (CTM) technique is a good candidate for aerospace and military missions. The total ionization dose (TID) effects on CTM cells with Al2O3/HfO2/Al2O3 (AHA) high-k gate stack structure under in-situ 10 keV x-rays are studied. The C–V characteristics at different radiation doses demonstrate that charge stored in the device continues to be leaked away during the irradiation, thereby inducing the shift of flatband voltage (Vfb). The dc memory window shows insignificant changes, suggesting the existence of good P/E ability. Furthermore, the physical mechanisms of TID induced radiation damages in AHA-based CTM are analyzed.

Impact of gate-to-source/drain misalignments on source-side injection Schottky barrier charge-trapping memory cells evaluated using numerical programming-trapping iterations

This work numerically elucidates the effects of gate-to-source/drain misalignments on source-side injection Schottky barrier charge-trapping memory cells. The coupling of Schottky barriers and trap charges generate particular Schottky barrier lowering and source-side injection, while the charge-coupled Schottky barriers must be considered concurrently with the precise positions of metallic source/drain junctions. Numerical programming-trapping iterations were employed to examine the distribution of electron injections and trapped charges in the charge-coupled cells, and to discuss the differences of physical mechanisms among the aligned, overlapped, and underlapped cells. The overlapped cells produce a mildly high programming and reading currents because of the shorter effective lengths. However, the underlapped cells suffer severely from the degradation of electron drain current, hot-carriers injection, and threshold-voltage shift because of widened tunneling barrier, reduced electric field, and invalid injection location. Mildly gate-to-source/drain overlap should be designed in Schottky barrier charge-trapping memories to avoid the underlapped offsets, ensuring favorable programming and reading performance.

Drain-induced Schottky barrier source-side hot carriers and its application to program local bits of nanowire charge-trapping memories

A new mechanism of drain-induced Schottky barrier lowering is reported experimentally for Schottky barrier nanowire devices. The strong drain-induced barrier lowering and associated source-side hot electrons were employed to program the localized bits of nanowire charge-trapping memory cells. For Schottky barrier nanowire devices, two different mechanisms of Schottky barrier lowering are classified: 1) gate-controlled and 2) drain-induced. In the drain-mode conduction, the lowering of Schottky source barrier relies on the drain voltage. The smaller gate voltage and the larger drain voltage are, the higher drain current is attained. The pure drain-induced current can locally program the nanowire charge-trapping cells at a drain voltage of 5–6 V. The decoupled forward and reverse reading curves confirm the trap charges are sorely programmed at the source-side region. This new drain-induced lowering mechanism provides a practical approach to program the multi-bit/cell NOR-type nanowire charge-trapping memories, and the drain-mode programming preserves excellent thermal retention and cycling endurance.

Enhanced memory effect via quantum confinement in 16 nm InN nanoparticles embedded in ZnO charge trapping layer

In this work, the fabrication of charge trapping memory cells with laser-synthesized indium-nitride nanoparticles (InN-NPs) embedded in ZnO charge trapping layer is demonstrated. Atomic layer deposited Al2O3 layers are used as tunnel and blocking oxides. The gate contacts are sputtered using a shadow mask which eliminates the need for any lithography steps. High frequency C-Vgate measurements show that a memory effect is observed, due to the charging of the InN-NPs. With a low operating voltage of 4 V, the memory shows a noticeable threshold voltage (Vt) shift of 2 V, which indicates that InN-NPs act as charge trapping centers. Without InN-NPs, the observed memory hysteresis is negligible. At higher programming voltages of 10 V, a memory window of 5 V is achieved and the Vt shift direction indicates that electrons tunnel from channel to charge storage layer.

Ti–Al–O nanocrystal charge trapping memory cells fabricated by atomic layer deposition

Charge trapping memory cells using Ti–Al–O (TAO) film as charge trapping layer and amorphous Al2O3 as the tunneling and blocking layers were fabricated on Si substrates by atomic layer deposition method. As-deposited TAO films were annealed at 700°C, 800°C and 900°C for 3min in N2 with a rapid thermal annealing process to form nanocrystals. High-resolution transmission electron microscopy and X-ray photoelectron spectroscopy were used to characterize the microstructure and band diagram of the heterostructures. The electrical characteristics and charge storage properties of the Al2O3/TAO/Al2O3/Si stack structures were also evaluated. Compared to 700°C and 900°C samples, the memory cells annealed at 800°C exhibit better memory performance with larger memory window of 4.8V at ±6V sweeping, higher program/erase speed and excellent endurance.

Reading Operation and Cell Scalability of Nonvolatile Schottky barrier Multibit Charge-Trapping Memory Cells

Using unique ambipolar conduction, a Schottky barrier multibit cell can be programmed using source-side electron injection and can be erased reversely using drain-side hole compensation. This paper numerically discusses the particular reading operation and cell scalability of the Schottky barrier multibit cell resulting from the presence of Schottky source/drain barriers. Forward and reverse reading schemes were examined to determine the multibit-cell state. Critical cell factors, such as channel length, Schottky barrier height, and electrode voltage, were examined to select appropriate structural parameters and operational conditions. Because of the unique Schottky source/drain barriers, the scaled Schottky barrier cell exhibits excellent short-channel immunity and retains the nature of cell reading, source-side programming, and drain-side erasing in a nanoscale regime. Preserving a compact stack-gate architecture and a thorough CMOS process, the Schottky barrier multibit cell serves as a promising candidate for use in nonvolatile embedded and commodity memory devices.

TaN and $\hbox{Al}_{2}\hbox{O}_{3}$ Sidewall Gate-Etch Damage Influence on Program, Erase, and Retention of Sub-50-nm TANOS nand Flash Memory Cells

The sidewall gate-etch damage influence on the electrical behavior of 48-nm TaN/AI <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> /SiN/SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /Si (TANOS) NAND charge-trapping memory cells is investigated in detail. This etch damage occurs at the sidewall of the high work-function TaN metal gate and high-k AI <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> blocking-oxide layers and adversely affects the electrical performance and the mechanical stability of small-ground-rule TANOS cells. Both issues could be solved for 48-nm TANOS cells by the introduction of a new integration scheme, which includes a removable encapsulation liner. This SiN liner protects the TaN sidewall from the etch damage during the aggressive AI <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> high-k etch process. The optimum of the 48-nm electrical cell performance was found for a 4-nm encapsulation liner thickness. In contrast to 48-nm TANOS cells, the encapsulation liner thickness does not affect the electrical performance of large 5-μm-long-and-wide memory cells. The memory cell performance dependence on the TANOS liner thickness and memory cell size is explained by a damaged AI <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> region approximately 3-4 nm thick at the block oxide side wall. As a result, the reported etch damage exhibits a new scaling issue for TANOS memory cells around the 20-nm technology node when the total encapsulation liner thickness approaches half of the memory cell length.

Characterisation of retention properties of charge-trapping memory cells at low temperatures

The density of states of deep level centers in silicon oxynitride layer of SONOS memory cells are calculated from temperature dependent retention measurement. The dominating charge loss mechanisms are direct trap-to-band tunneling (TB) and thermally stimulated emission (TE). Retention measurements at low temperatures (80 – 300K) will be dominated by TE from more "shallow" traps with energies below 1eV and by TB. Taking into account both independent and rival processes the density of states could be calculated self consisting. The results are in excellent agreement with elsewhere published data.

Carriers recombination processes in charge trapping memory cell by simulation

We have evaluated the effects of recombination processes in a charge storage layer, either between trapped electrons and trapped holes or between trapped carriers and free carriers, on charge trapping memory cell's performances by numerical simulation. Recombination is an indispensable mechanism in charge trapping memory. It helps charge convert process between negative and positive charges in the charge storage layer during charge trapping memory programming/erasing operation. It can affect the speed of programming and erasing operations.

Localized Charge Trapping Memory Cells in a 63 nm Generation with Nanoscale Epitaxial Cobalt Salicide Buried Bitlines

AbstractA 63nm Twin Flash memory cell with a size of 0.0225μm2 per 2 (or 4) bits is presented. To achieve small cell areas, a buried bit line and an aggressive gate length of 100 nm are the key features of this cell together with a minimum thermal budget processing. A novel epitaxial CoSi2 process allows the salicidation of local buried bitlines with only a few tens of nanometer width.

Charge-trapping memory cell of SiO2∕SiN∕high-k dielectric Al2O3 with TaN metal gate for suppressing backward-tunneling effect

We present a device structure of SiO2∕SiN∕Al2O3 (SANOS) with tantalum nitride (TaN) metal gate. When TaN metal gate is applied for the SANOS structure instead of commonly used n-type poly-silicon, the unwanted backward Fowler–Nordheim tunneling current of electron through the top oxide is significantly suppressed owing to its higher work function and better compatibility with high-k dielectrics. As a result, the program∕erase speed is significantly improved and the erase threshold voltage (VTH) can be obtained to be negative voltage of −3.5V.