Reading Operation and Cell Scalability of Nonvolatile Schottky barrier Multibit Charge-Trapping Memory Cells

Abstract

Using unique ambipolar conduction, a Schottky barrier multibit cell can be programmed using source-side electron injection and can be erased reversely using drain-side hole compensation. This paper numerically discusses the particular reading operation and cell scalability of the Schottky barrier multibit cell resulting from the presence of Schottky source/drain barriers. Forward and reverse reading schemes were examined to determine the multibit-cell state. Critical cell factors, such as channel length, Schottky barrier height, and electrode voltage, were examined to select appropriate structural parameters and operational conditions. Because of the unique Schottky source/drain barriers, the scaled Schottky barrier cell exhibits excellent short-channel immunity and retains the nature of cell reading, source-side programming, and drain-side erasing in a nanoscale regime. Preserving a compact stack-gate architecture and a thorough CMOS process, the Schottky barrier multibit cell serves as a promising candidate for use in nonvolatile embedded and commodity memory devices.