Charge Trapping In Oxide Research Articles

Mechanisms of spontaneous recovery in DC gate bias stressed power VDMOSFETs

The effects of spontaneous recovery on threshold voltage and channel carrier mobility in DC gate bias stressed power VDMOSFETs, as well as the underlying changes in gate oxide-trapped charge and interface trap densities, are analysed in terms of the mechanisms responsible. Various mechanisms, including drift of oxide-trapped charge to the SiO2–Si interface, charge neutralisation, interface trap redistribution and electrochemical reactions near the interface are considered, in order to explain the experimental results. A major difference in the results for post-stress recovery obtained by subthreshold midgap and single transistor mobility techniques, both indicating mostly decrease in interface trap and oxide-trapped charge densities and the charge pumping technique, which signified a remarkable post-stress increase of true interface trap density, is ascribed to both interface trap redistribution within the silicon bandgap and to the inability of the former two techniques to assess the contribution of border traps to the estimated densities of interface traps. Drift of positive oxide charge to the interface, accompanied by subsequent charge neutralisation and interface trap redistribution, is found to dominate in the early stage of post-stress recovery, whereas the chain of electrochemical reactions involving hydrogen species (passivation of interface traps, dissociation of interfacial trap precursors, hydrogen dimerisation and cracking at charged oxide traps) is shown to become more important in the advanced stage of recovery.

Radiation degradation model of metal-oxide-semiconductor field effect transistor based on pre-irradiation 1/f noise

Based on metal-oxide-semiconductor field effect transistor (MOSFET) noise theory of carrier number fluctuation and mobility fluctuation， a quantitative mathematic model between pre-irradiation 1/f noise parameters and post-irradiation threshold voltage drift due to oxide traps and interface traps is established. It agrees well with the experimental results. This model shows that 1/f noise in MOSFET is priginates from the random trapping/detrapping processes between oxide traps and the channel， which causes fluctuations in both the number and the mobility of channel carriers. So pre-irradiation 1/f noise magnitude is directly proportional to post-irradiation oxide-trap charge. The results not only explain the correlation between MOSFET pre-irradiation 1/f noise power spectral density and radiation degradation in theory， but also provide the theory for forecasting MOSFET radiation-resistant capability.

Hot-carrier reliability in high-voltage lateral double-diffused MOS transistors

With the continuing scaling of metal–oxide–semiconductor (MOS) devices, the hot-carrier (HC)-induced device degradation has become a major reliabiliy concern in sub- and deep-submicrometre MOS field-effect transistors (MOSFETs) and lateral double-diffused MOSFETs (LDMOSFETs). It is believed that the degradation is mainly due to the effects of the generated oxide-trapped charges and interface traps at the Si/SiO2 interface. In general, the large electric field is strongly localised in a well-defined region; therefore carrier injection and interface-trap creation are similarly concentrated. The strongly inharmonious characters of HC injection and resulting damage present a considerable challenge to both experimental and modelling efforts.The HC degradation behaviour of an n-channel LDMOS transistor is investigated under various stress conditions. By applying variable base charge pumping experiments, a consistent picture of the degradation mechanism can be depicted. HC-induced interface traps are generated in the channel region of the device, in the drift region below the thick field oxide and at the bird's beak edge. The latter is shown to dominate the degradation of Idlin, which is the most critical parameter concerning HC lifetime in this specific device.

Radiation Induced Charge Trapping in Ultrathin ${\rm HfO}_{2}$-Based MOSFETs

Radiation induced charge trapping in ultrathin HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> -based n-channel MOSFETs is characterized as a function of dielectric thickness and irradiation bias following exposure to 10 keV X-rays and/or constant voltage stress. Positive and negative oxide-trap charges are observed, depending on irradiation and bias stress conditions. No significant interface-trap buildup is found in these devices under these irradiation and stress conditions. Enhanced oxide-charge trapping occurs in some cases for simultaneous application of constant voltage stress and irradiation, relative to either type of stress applied separately. Room temperature annealing at positive bias after irradiation of transistors with thicker gate dielectric films leads to positive oxide-trapped charge annihilation and/or neutralization in these devices, and net electron trapping. The oxide thickness dependence of the radiation response confirms the extreme radiation tolerance of thin HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> dielectric layers of relevance to device applications, and suggests that hole traps in the thicker layers are located in the bulk of the dielectric. A revised methodology is developed to estimate the net effective charge trapping efficiency, f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ot</sub> , for high-kappa dielectric films. As a result, estimates of f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ot</sub> for Hf silicate capacitors and Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> transistors in previous work are reduced by up to 18%.

Total Dose and Bias Temperature Stress Effects for HfSiON on Si MOS Capacitors

We have performed an experimental study of the effects of ionizing radiation and bias-temperature stress on Si MOS devices with HfSiON gate dielectrics. We compare the responses of homogeneous high-SiN films and low-SiN films that contain crystalline HfO. We observe that the low-SiN films are more sensitive to ionizing radiation than the high-SiN films. In particular, the low-SiN film that includes crystalline HfO is especially vulnerable to electron trapping due to substrate injection under positive irradiation bias. Both film types exhibit reduced radiation-induced charge trapping relative to previous Hf silicates. The high-SiN film exhibits less radiation-induced net oxide-trap charge density than earlier Hf silicate films processed without nitride. We also find that these devices are relatively robust against bias-temperature stress instabilities. Consistent with the radiation response, the low-SiN devices also display elevated levels of charge trapping relative to the high-SiN devices during bias-temperature stress.

Off-State Avalanche-Breakdown-Induced on-Resistance Degradation in Lateral DMOS Transistors

In this letter, on-resistance R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> degradation in lateral double-diffused MOS transistors is observed when the device is operated under off-state avalanche-breakdown condition. Although interface states and positive oxide-trapped charges are created near the drain, interface-state generation is identified to be the main degradation mechanism. Technology computer-aided design simulation suggests that the driving force of damage is breakdown-induced hole injection. Experimental data show that R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> degradation has the tendency to saturate, in agreement with the saturation of interface-state generation and oxide-trapped charges data extracted by charge-pumping measurement.

On the electrical stress-induced oxide-trapped charges in thin HfO2∕SiO2 gate dielectric stack

Oxide charge buildup and its generation kinetics during constant voltage stress in TaN∕HfO2∕SiO2∕p-Si structures have been experimentally investigated. From the oxide charge relaxation experiments, nature and energy location of the as-fabricated intrinsic hole traps in the gate stack have also been determined. Our measurement results indicate that the dispersive proton transport through the interfacial SiO2 contributes larger than hole trapping in positive charge buildup in the stack. From the bias temperature stress measurement results in both control oxide and HfO2∕SiO2 stacks, we have identified overcoordinated [Si2=OH]+ centers as the proton-induced defects located in the interfacial SiO2 layer of the stack. Finally, an empirical equation is proposed to explain the stress-induced oxide positive charge buildup.

Negative bias temperature instabilities in sequentially stressed and annealed p-channel power VDMOSFETs

The effects of intermittent low-bias annealing on NBT stress-induced threshold voltage shifts in p-channel VDMOSFETs are analysed in terms of mechanisms responsible for underlying changes in the densities of gate oxide-trapped charge and interface traps. Negative bias annealing after an initial NBT stress appears to freeze the initial degradation. Alternatively, either positive or zero bias removes the portion of stress-generated oxide-trapped charge and creates new reversible component of interface traps, while each repeated NBT stress regenerates the oxide-trapped charge and removes the reversible component of interface traps. The post-stress generation of interface traps under positive oxide field is ascribed to the processes at SiO 2/Si interface arising from the reversed drift direction of positively charged species, which are not likely to occur under negative gate bias. Despite all these phenomena, intermittent annealing does not seem to affect the device lifetime.

Structural and electrical properties of high-κ Bi2Mg2∕3Nb4∕3O7 pyrochlore films on silicon for possible gate dielectric applications

Bi 2 Mg 2 ∕ 3 Nb 4 ∕ 3 O 7 pyrochlore films were deposited on p-type Si (100) substrates using radio frequency reactive magnetron sputtering technique. Rapid thermal annealing (RTA) in O2 ambient followed by RTA in N2 ambient was carried out. The structural, morphological, and chemical bonding features of these films were studied by x-ray diffraction, scanning electron microscopy, atomic force microscopy, and x-ray photoelectron spectroscopy. All the films exhibit smooth, homogeneous, continuous, crack free, and dense films surfaces with root-mean-square roughness values in the range of 1.91−4.16 Å. The films show high crystallization temperature at about 900 °C. High temperature annealing gives rise to more oxygen incorporation in the films with probable formation of silicate type bonding at the interface. Effective oxide charge density, flatband voltage, hysteresis, oxide trap charge density, and interface state density values are comparable to those of some of the most widely investigated high-k gate dielectrics. The values decrease with increasing annealing temperature. A minimum leakage current density of the order of ∼10−6 A∕cm2 at a bias voltage of −1 V has been obtained even after annealing at 800 °C. All the annealed films show high breakdown field values of more than 5 MV/cm.

Influence of polysilicon film thickness on radiation response of advanced excimer laser annealed polycrystalline silicon thin film transistors

This paper presents results of gamma irradiation effects in advanced excimer laser annealed polysilicon thin film transistors realized in polysilicon films having different thicknesses. It is shown that the thickness of polysilicon film has a strong influence on the degradation level of electrical parameters of irradiated thin film transistors, offering a possibility for optimization of these devices with the purpose to increase their reliability. The analysis was performed by monitoring of important electrical parameters, as well as of the density of irradiation induced oxide trapped charge and interface traps at the oxide–polysilicon interface, and the density of polysilicon grain boundary traps in the channel region of the transistors.

Total Dose Response of Ge MOS Capacitors With HfO$_{2}$/Dy$_{2}$O$_{3}$ Gate Stacks

We report the results of total ionizing dose radiation tests on germanium-substrate MOS capacitors with HfO2/Dy2O3 gate dielectrics with effective oxide thicknesses of ~1.9 and 1.1 nm. There are significant densities of border traps before irradiation, and no measurable changes in device response after 10 Mrad(SiO2) exposure. We attribute the lack of net oxide charge trapping to equal electron and hole trapping and/or charge neutralization via gate leakage current. The introduction of Dy2O3 evidently leads to reduced charge trapping in these HfO2/Dy2O3 dielectrics relative to devices with only HfO2.

Oxide-Trapped Charges Induced by Electrostatic Discharge Impulse Stress

The characteristics of oxide-trapped charges Qot induced by electrostatic discharge high-field current impulse stress, i.e., transmission line pulsing (TLP), were studied. It was observed that for a 3.2-nm-thin oxide, the centroid evolution and the critical density of positive oxide-trapped charges Qot + to trigger oxide breakdown are about the same between dc and TLP impulse stresses. These results are consistent with the existing models of stress-induced trapping charges and hole-induced oxide breakdown. However, different behaviors of Qot and centroid were found for 14-nm-thick oxides subjected to different stress tests. TLP impulse stress generates far less amount of negative oxide- trapped charges Qot - than dc stress, and the positive oxide-trapped charges finally dominate over the negative oxide-trapped charges. This impulse stress imposes a high density and transient current on the oxide, which induces traps at the tunneling distance locally. The hotter injected electrons generate more efficient hole trappings to provoke breakdown with lower density of oxide-trapped charges in comparison with dc stress test.

Electrical Properties of ZrO&lt;sub&gt;2&lt;/sub&gt; Capacitor Dielectrics Deposited by rf Magnetron Sputtering

The structure and electrical properties of ZrO2 dielectric thin films deposited by rf magnetron sputtering were investigated. The fixed oxide charge and interface trap density at the ZrO2/Si interface is substantially decreased by annealing at 500 C. Annealing treatment also enhances the quality of the film by reducing leakage current. The carrier transport mechanism in the ZrO2 film is dominated by thermionic emission.

Thermal annealing effect on electrical properties of metal nitride gate electrodes with hafnium oxide gate dielectrics in nano-metric MOS devices

Electrical properties of hafnium oxide (HfO 2) gate dielectric with various metal nitride gate electrodes, i.e., tantalum nitride (TaN), molybdenum nitride (MoN), and tungsten nitride (WN), were studied over a range of HfO 2 thicknesses, e.g., 2.5–10 nm, and post-metal annealing (PMA) temperatures, e.g., 600 °C to 800 °C. The work function of the nitride gate electrode was dependent on the material and the post-metal annealing (PMA) temperature. The scanning transmission electron microscopy technique is used to observe the effect of PMA on the interfacial gate dielectric thickness. After high-temperature annealing, the metal nitride gates were suitable for NMOS. At the same PMA temperature, the oxide-trapped charges increased and the interface state densities decreased with the increase of the HfO 2 thickness for TaN and WN gate electrodes. However, for MoN gate electrode the interface state density is almost independent of film thickness. Therefore, dielectric properties of the HfO 2 high- k film depend not only on the metal nitride gate electrode material but also the post-metal annealing condition as well as the film thickness. During constant voltage stress of the MOS capacitors, an increase in the time-dependent gate leakage current is also observed.

Mechanism of Static and Dynamic Bias Temperature Instability in p- and n-MOSFETs

The BTI-induced degradation of device performance has been ascribed to interface trap generation (ΔNit) and oxide charge buildup (ΔNot) at or near the SiO2/Si interface. Moreover, it has been widely recognized that degradation under dynamic BTI stressing may differ from that under static stressing. In this paper, our recent studies on BTI are reviewed. First, a modified direct-current current-voltage (DCIV) method is proposed, which can monitor ΔNit and ΔNot separately, and is independent on the measurement temperature. Second, negative BTI in pMOSFETs with ultrathin plasma-nitrided SiON gate dielectrics is systematically studied, as well as the effect of nitrogen concentration, using the modified DCIV method. Third, dynamic BTI with is studied at various stressing configurations. A transient degradation enhancement is observed upon quick gate voltage reversal from the accumulation bias to the inversion bias. Finally, a modified reaction-diffusion model is proposed to consistently explain the observed static and dynamic BTI behavior.

Random-Telegraph-Signal Noise and Device Variability in Ballistic Nanotube Transistors

In field-effect transistors (FETs), charge trapping in the gate oxide is known to cause low-frequency noise and threshold shifts. Here we calculate the effect of single trapped charges in a carbon nanotube FET, using the nonequilibrium Greens function method in a tight-binding approximation. We find that a single charge can shift and even rescale the entire transfer characteristic of the device. This can explain both the large "random telegraph signal" noise and the large variations between nominally identical devices. We examine the dependence on both the thickness and dielectric constant of the gate dielectric, suggesting routes to reduce electrical noise.

Strong Improvement of the Electroluminescence Stability of SiO[sub 2]:Gd Layers by Potassium Co-implantation

Metal-oxide-silicon-based light-emitting diodes with Gd-implanted SiO 2 layers exhibit strong ultraviolet electroluminescence at 316 nm coming from Gd 3+ ions. Co-implantation of potassium ions into the SiO 2 :Gd layer leads to elimination of the luminescent peak from point defects in SiO 2 layers. The electropositive potassium ions compensate the negative charge trapping in the gate oxide and thus improve the electrical stability of the ultraviolet emission from Gd 3+ ions. The operating time of the devices was increased more than 30 times by using potassium co-implantation and millisecond flash lamp annealing.

Ultrathin Si capping layer suppresses charge trapping in HfOxNy∕Ge metal-insulator-semiconductor capacitors

In this study the authors investigated the Ge outdiffusion characteristics of HfOxNy∕Ge metal-insulator-semiconductor capacitors to determine their charge trapping behavior. Capping the Ge substrate with an ultrathin Si layer inhibits the incorporation of Ge into the high-k bulk dielectric in the form of GeOx, thereby diminishing the resultant oxide charge trapping. The thermal stability of the entire capacitor structure was also improved after performing an additional Si passivation process.

A 1/f noise based research of radiation induced interface trap buildup process

Based on the two-step interface trap buildup model and the statistical thermodynamics mechanism of point defects in solids, a relation between the radiation induced increase of oxide hole-traps and the buildup of interface traps in MOSFET is proposed. Then, based on the correlation between pre-irradiation 1/f noise power spectral density and post-irradiation oxide-trap charge, a sim-empirical expression of pre-irradiation 1/f noise and post-irradiation interface traps buildup is established which agrees well with the experimental results. This model shows that the process of interface trap buildup was influenced by the increasing of oxide hole-traps that could dissociated hydrogen into proton under irradiation. So, the magnitude of pre-irradiation 1/f noise is directly proportional to post-irradiation interface-trap charge and sub-threshold slope. Our results not only proves that the 1/f noise can play a important role in MOSFET irradiation effects, but also proves a new nondestructive method to estimate MOSFET radiation response.

Charging and discharging processes of carbon nanotubes probed by electrostatic force microscopy

Electrostatic properties of individually separated single-walled carbon nanotubes (SWCNTs), double-walled carbon nanotubes (DWCNTs), and multiwalled carbon nanotubes (MWCNTs) deposited on insulating layers have been investigated by charge injection and electric force microscopy (EFM) experiments. Delocalized charge patterns are observed along the CNTs upon local injection from the EFM tip, corresponding to (i) charge storage in the nanotubes and to (ii) charge trapping in the oxide layer along the nanotubes. The two effects are dissociated easily for CNTs showing abrupt discharge processes in which the charge stored in the CNT are field emitted back to the EFM tip, while trapped oxide charge can subsequently be imaged by EFM, clearly revealing field-enhancement patterns at the CNT caps. The case of continuous discharge processes of SWCNTs, DWCNTs, and MWCNTs is discussed, as well as the evolution of the discharge time constants with respect to the nanotube diameter.