Charge Trapping Sites Research Articles

Intrinsic electron trapping in amorphous oxide

We demonstrate that electron trapping at intrinsic precursor sites is endemic in non-glass-forming amorphous oxide films. The energy distributions of trapped electron states in ultra-pure prototype amorphous (a)-HfO2 insulator obtained from exhaustive photo-depopulation experiments demonstrate electron states in the energy range of 2–3 eV below the oxide conduction band. These energy distributions are compared to the results of density functional calculations of a-HfO2 models of realistic density. The experimental results can be explained by the presence of intrinsic charge trapping sites formed by under-coordinated Hf cations and elongated Hf–O bonds in a-HfO2. These charge trapping states can capture up to two electrons, forming polarons and bi-polarons. The corresponding trapping sites are different from the dangling-bond type defects responsible for trapping in glass-forming oxides, such as SiO2, in that the traps are formed without bonds being broken. Furthermore, introduction of hydrogen causes formation of somewhat energetically deeper electron traps when a proton is immobilized next to the trapped electron bi-polaron. The proposed novel mechanism of intrinsic charge trapping in a-HfO2 represents a new paradigm for charge trapping in a broad class of non-glass-forming amorphous insulators.

Comparison With Nitride Interface Defects and Nanocrystals for Charge Trapping Layer Nanowire Gate-All-Around Nonvolatile Memory Performance

This paper demonstrates novel silicon–oxide–nitride–nitride–oxide–silicon (SONNOS) and silicon-oxide-nanocrystals-oxide-silicon (SOncOS) nonvolatile memory (NVM) that is based on nanowires gate-all-around (GAA) structure. SONNOS and SOncOS NVM exploit doubly stacked Si3N4 (NN) interface defects and silicon nanocrystals as charge trapping layers, respectively. Experimental results reveal that SONNOS NVM has superior memory characteristics than SOncOS NVM. With respect to memory reliability, the SONNOS NVM retains 86% memory window after 104 program/erase cycles, and the memory window retains 42% of the originally stored charge after ten years. Such doubly stacked Si3N4 layers provide additionally charge trapping sites in CTL, improving the memory performance of NVM. In the future, SONNOS GAA NVMs will be easily integrated in 3-D nand flash memory applications.

Superfast Room-Temperature Activation of SnO2 Thin Films via Atmospheric Plasma Oxidation and their Application in Planar Perovskite Photovoltaics.

The power conversion efficiency (PCE) of perovskite solar cells (PSCs) has now exceeded 20%; thus, research focus has shifted to establishing the foundations for commercialization. One of the pivotal themes is to curtail the overall fabrication time, to reduce unit cost, and mass-produce PSCs. Additionally, energy dissipation during the thermal annealing (TA) stage must be minimized by realizing a genuine low-temperature (LT) process. Here, tin oxide (SnO2 ) thin films (TFs) are formulated at extremely high speed, within 5 min, under an almost room-temperature environment (<50 °C), using atmospheric Ar/O2 plasma energy (P-SnO2 ) and are applied as an electron transport layer of a "n-i-p"-type planar PSC. Compared with a thermally annealed SnO2 TF (T-SnO2 ), the P-SnO2 TF yields a more even surface but also outstanding electrical conductivity with higher electron mobility and a lower number of charge trap sites, consequently achieving a superior PCE of 19.56% in P-SnO2 -based PSCs. These findings motivate the use of a plasma strategy to fabricate various metal oxide TFs using the sol-gel route.

Solution Processed Organic Transistor Nonvolatile Memory With a Floating-Gate of Carbon Nanotubes

In this letter, an organic field-effect transistor nonvolatile memory (NVM), based on single-walled carbon nanotubes (SWNTs) as a nano floating-gate, is demonstrated, for which a four-layer stacked core architecture was processed by following the sequential solution spin-coating method. The SWNTs, separated by spin-coating, are distributed in the matrix of copolymer poly (styrene-block-paraphenylene) to act as the charge trapping sites. The memory of the floating-gate organic transistor so prepared exhibits excellent NVM characteristics,with a large memory window of 26.7 V, memory on/off ratio larger than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> , stable charge storage retention capability for over 3 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> s with a memory on/off ratio over 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , and the reliable memory endurance property of over 500 Hz.

Solution-Processed Wide-Bandgap Organic Semiconductor Nanostructures Arrays for Nonvolatile Organic Field-Effect Transistor Memory.

In this paper, the development of organic field-effect transistor (OFET) memory device based on isolated and ordered nanostructures (NSs) arrays of wide-bandgap (WBG) small-molecule organic semiconductor material [2-(9-(4-(octyloxy)phenyl)-9H-fluoren-2-yl)thiophene]3 (WG3 ) is reported. The WG3 NSs are prepared from phase separation by spin-coating blend solutions of WG3 /trimethylolpropane (TMP), and then introduced as charge storage elements for nonvolatile OFET memory devices. Compared to the OFET memory device with smooth WG3 film, the device based on WG3 NSs arrays exhibits significant improvements in memory performance including larger memory window (≈45 V), faster switching speed (≈1 s), stable retention capability (>104 s), and reliable switching properties. A quantitative study of the WG3 NSs morphology reveals that enhanced memory performance is attributed to the improved charge trapping/charge-exciton annihilation efficiency induced by increased contact area between the WG3 NSs and pentacene layer. This versatile solution-processing approach to preparing WG3 NSs arrays as charge trapping sites allows for fabrication of high-performance nonvolatile OFET memory devices, which could be applicable to a wide range of WBG organic semiconductor materials.

Synthesis of High-Crystallinity DPP Polymers with Balanced Electron and Hole Mobility

We review the Stille coupling synthesis of P(DPP2OD-T) (Poly[[2,5-di(2-octyldodecyl)pyrrolo[3,4-c]pyrrole-1,4(2H,5H)-dione-3,6-diyl]-alt-[2,2′:5′,2″-terthiophene-5,5″-diyl]]) and show that high-quality, high molecular weight polymer chains are already obtained after as little as 15 min of reaction time. The results of UV–vis spectroscopy, grazing incidence wide-angle X-ray scattering (GIWAXS), and atomic force microscopy show that longer reaction times are unnecessary and do not produce any improvement in film quality. We achieve the best charge transport properties with polymer batches obtained from short reaction times and demonstrate that the catalyst washing step is responsible for the introduction of charge-trapping sites for both holes and electrons. These trap sites decrease the charge injection efficiency, strongly reducing the measured currents. The careful tuning of the synthesis allows us to reduce the reaction time by more than 100 times, achieving a more environmentally friendly, less costly ...

Synthesis of Cr3+-doped TiO2 nanoparticles: characterization and evaluation of their visible photocatalytic performance and stability

ABSTRACTCr3+-doped TiO2 nanoparticles (Ti-Cr) were synthesized by microwave-assisted sol-gel method. The Ti-Cr catalyst was characterized by X-ray diffraction, ultraviolet-visible diffuse reflectance spectroscopy, N2 adsorption-desorption analysis, Raman spectroscopy, scanning electron microscopy, transmission electron microscopy, photoluminescence spectroscopy, X-ray photoelectron spectroscopy (XPS) and zetametry. The anatase mesoporous Ti-Cr material exhibited a specific surface area of 54.5 m2/g. XPS analysis confirmed the proper substitution of Ti4+ cations by Cr3+ cations in the TiO2 matrix. The particle size was of average size of 17 nm for the undoped TiO2 but only 9.5 nm for Ti-Cr. The Cr atoms promoted the formation of hydroxyl radicals and modified the surface adsorptive properties of TiO2 due to the increase in surface acidity of the material. The photocatalytic evaluation demonstrated that the Ti-Cr catalyst completely degraded (4-chloro-2-methylphenoxy) acetic acid under visible light irradiation, while undoped TiO2 and P25 allowed 45.7% and 31.1%, respectively. The rate of degradation remained 52% after three cycles of catalyst reuse. The higher visible light photocatalytic activity of Ti-Cr was attributed to the beneficial effect of Cr3+ ions on the TiO2 surface creating defects within the TiO2 crystal lattice, which can act as charge-trapping sites, reducing the electron−hole recombination process.

Bulky side chain effect of poly(N‐vinylcarbazole)‐based stacked polymer electrets on device performance parameters of transistor memories

ABSTRACTThree poly(N‐vinylcarbazole) (PVK)‐based polymer electrets were synthesized through Friedel‐Crafts postfunctionalization for the function of charge storage in nonvolatile organic field effect transistor (OFET) memory devices. The bulky side chain effect of these stacked polymer electrets on the morphology, water contact angles, and memory characteristics were examined with regard to those of precursor PVK. The introduction of steric hindrance groups could interrupt the large length of π‐stacked structures in PVK and block the form of region‐regular structures from region‐random on external electric field. As a result, the memories based on the three modified polymers exhibited approximate memory windows of 32 V increased by 13 V with respect to PVK. Besides, the write‐read‐erase‐read cycles stability of the modified polymers was superior to that of PVK. Furthermore, we found that the holes were mainly located in the region of local π‐stacked structures and bulky π‐conjugated groups also acted as additional electron trapping sites. Molecular engineering of charge trapping site with tunneling polymers will be a promise strategy for the advance of transistor memory. © 2017 Wiley Periodicals, Inc. J. Polym. Sci., Part A: Polym. Chem. 2017, 55, 3554–3564

Achieving tunable memory performance from nonvolatile to volatile by altering the trap depth of charge trapping sites in functional imides containing carbazole moieties

In this work, two functional imides were designed and synthesized to elucidate the influence of charge trap depth on the memory behavior. Two dianhydrides, 3,3′,4,4'-diphenylsulfonetetracarboxylic dianhydride and 4,4'-(hexafluoroisopropylidene)diphthalic anhydride were selected as the electron acceptor considering their functional moieties of different charge-trapping depth and electron-withdrawing ability. Electrical characterization indicated that the memory devices based on the two imides exhibited nonvolatile write once read many times (WORM) memory behavior and volatile static random access memory (SRAM) behavior. Mechanisms associated with the distinct memory effect were demonstrated based on the molecular simulation. Analysis results indicated that charge trapping process is responsible for the electrical bistability and the different depth of charge-trapping sites in the two imides accounts for the distinct memory behavior of corresponding memory devices. Meanwhile, the two memory devices both show excellent long term operation stability. This paper not only reports two novel memory materials but also provided some guiding principle to the design of organic based memory devices.

High-Performance Nonvolatile Organic Field-Effect Transistor Memory Based on Organic Semiconductor Heterostructures of Pentacene/P13/Pentacene as Both Charge Transport and Trapping Layers.

Nonvolatile organic field‐effect transistor (OFET) memory devices based on pentacene/N,N′‐ditridecylperylene‐3,4,9,10‐tetracarboxylic diimide (P13)/pentacene trilayer organic heterostructures have been proposed. The discontinuous n‐type P13 embedded in p‐type pentacene layers can not only provide electrons in the semiconductor layer that facilitates electron trapping process; it also works as charge trapping sites, which is attributed to the quantum well‐like pentacene/P13/pentacene organic heterostructures. The synergistic effects of charge trapping in the discontinuous P13 and the charge‐trapping property of the poly(4‐vinylphenol) (PVP) layer remarkably improve the memory performance. In addition, the trilayer organic heterostructures have also been successfully applied to multilevel and flexible nonvolatile memory devices. The results provide a novel design strategy to achieve high‐performance nonvolatile OFET memory devices and allow potential applications for different combinations of various organic semiconductor materials in OFET memory.

Solution Processed Top-Gate High-Performance Organic Transistor Nonvolatile Memory With Separated Molecular Microdomains Floating-Gate

In this letter, a top-gate high-performance floating-gate organic field-effect transistor nonvolatile memory (FG-OFET-NVM), where the four-layer stacked core architecture is processed by a successive solution spin-coating method, is demonstrated. The floating-gate layer is prepared by spin-coating from a blend solution consisting of poly(styrene) (PS) and 6,13-bis(triisopropylsilylethynyl)pentacene (TIPS-Pen). As a result of phase separation, TIPS-Pen aggregates and forms many separated microdomains, which uniformly distribute in thematrix of PS as the charge-trapping sites. The optimal FG-OFET-NVM exhibits excellent memory characteristics, with a large memory window of 26 V, a desired reading voltage of 0 V, a memory ON/OFF ratio larger than 3500, programming/erasing switching endurance over 500 cycles, and good charge-storage retention with a memory ON/OFF ratio larger than 103 over 5000 s.

Suppression of space charge in crosslinked polyethylene filled with poly(stearyl methacrylate)-grafted SiO2 nanoparticles

Incorporating inorganic nanoparticles (NPs) into polymer matrices provides a promising solution for suppressing space charge effects that can lead to premature failure of electrical insulation used in high voltage direct current engineering. However, realizing homogeneous NP dispersion is a great challenge especially in high-molecular-weight polymers. Here, we address this issue in crosslinked polyethylene by grafting matrix-compatible polymer brushes onto spherical colloidal SiO2 NPs (10–15 nm diameter) to obtain a uniform NP dispersion, thus achieving enhanced space charge suppression, improved DC breakdown strength, and restricted internal field distortion (≤10.6%) over a wide range of external DC fields from −30 kV/mm to −100 kV/mm at room temperature. The NP dispersion state is the key to ensuring an optimized distribution of deep trapping sites. A well-dispersed system provides sufficient charge trapping sites and shows better performance compared to ones with large aggregates. This surface ligand strategy is attractive for future nano-modification of many engineering insulating polymers.

Abnormal Multiple Charge Memory States in Exfoliated Few-Layer WSe2 Transistors.

To construct reliable nanoelectronic devices based on emerging 2D layered semiconductors, we need to understand the charge-trapping processes in such devices. Additionally, the identified charge-trapping schemes in such layered materials could be further exploited to make multibit (or highly desirable analog-tunable) memory devices. Here, we present a study on the abnormal charge-trapping or memory characteristics of few-layer WSe2 transistors. This work shows that multiple charge-trapping states with large extrema spacing, long retention time, and analog tunability can be excited in the transistors made from mechanically exfoliated few-layer WSe2 flakes, whereas they cannot be generated in widely studied few-layer MoS2 transistors. Such charge-trapping characteristics of WSe2 transistors are attributed to the exfoliation-induced interlayer deformation on the cleaved surfaces of few-layer WSe2 flakes, which can spontaneously form ambipolar charge-trapping sites. Our additional results from surface characterization, charge-retention characterization at different temperatures, and density functional theory computation strongly support this explanation. Furthermore, our research also demonstrates that the charge-trapping states excited in multiple transistors can be calibrated into consistent multibit data storage levels. This work advances the understanding of the charge memory mechanisms in layered semiconductors, and the observed charge-trapping states could be further studied for enabling ultralow-cost multibit analog memory devices.

Simple but Effective Way To Enhance Photoelectrochemical Solar-Water-Splitting Performance of ZnO Nanorod Arrays: Charge-Trapping Zn(OH)2 Annihilation and Oxygen Vacancy Generation by Vacuum Annealing.

This study presents an effective and the simplest method to substantially improve the photoelectrochemical water-splitting ability of hydrothermally grown ZnO nanorod arrays (NRAs). In the hydrothermal growth of ZnO NRAs, unwanted Zn(OH)2 species are formed, which act as trapping sites of photoexcited charges. We found that those inherent charge-trapping sites could be annihilated by the desorption of the hydroxyl groups upon vacuum annealing above 200 °C, which resulted in an enhancement of the charge-separation efficiency and photocurrent density. Another drastic increase in the photocurrent density occurred when ZnO NRAs were treated with annealing at higher temperature (700 °C), which can be attributed to the introduced oxygen vacancies acting as shallow donors in the ZnO crystal lattice. The removal of the charge-trapping Zn(OH)2 and the generation of oxygen vacancies were confirmed by photoluminescence (PL) and XPS analyses. The ZnO NRAs treated by this simple method yield a photocurrent density of 600 μA/cm2 at 1.23 VRHE under 1 sun illumination, which is 20 times higher than that obtained from as-grown ZnO NRAs. This study presents a highly efficient way of increasing the bulk electric conductivity and photoelectrochemical activity of metal oxide nanorods without requiring the introduction of any extrinsic dopants.

Integration of ammonia-plasma-functionalized graphene nanodiscs as charge trapping centers for nonvolatile memory applications

Graphene nanodiscs (GNDs), functionalized using NH3 plasma, as charge trapping sites (CTSs) for non-volatile memory applications have been investigated in this study. The fabrication process relies on the patterning of Au nanoparticles (Au-NPs), whose thicknesses are tuned to adjust the GND density and size upon etching. A GND density as high as 8 × 1011 cm−2 and a diameter of approximately 20 nm are achieved. The functionalization of GNDs by NH3 plasma creates NH+ functional groups that act as CTSs, as observed by Raman and Fourier transform infrared spectroscopy. This inherently enhances the density of CTSs in the GNDs, as a result, the memory window becomes more than 2.4 V and remains stable after 104 operating cycles. The charge loss is less than 10% for a 10-year data retention testing, making this low-temperature process suitable for low-cost non-volatile memory applications on flexible substrates.

Grain Boundary Induced Bias Instability in Soluble Acene-Based Thin-Film Transistors.

Since the grain boundaries (GBs) within the semiconductor layer of organic field-effect transistors (OFETs) have a strong influence on device performance, a substantial number of studies have been devoted to controlling the crystallization characteristics of organic semiconductors. We studied the intrinsic effects of GBs within 5,11-bis(triethylsilylethynyl) anthradithiophene (TES-ADT) thin films on the electrical properties of OFETs. The GB density was easily changed by controlling nulceation event in TES-ADT thin films. When the mixing time was increased, the number of aggregates in as-spun TES-ADT thin films were increased and subsequent exposure of the films to 1,2-dichloroethane vapor led to a significant increase in the number of nuleation sites, thereby increasing the GB density of TES-ADT spherulites. The density of GBs strongly influences the angular spread and crystallographic orientation of TES-ADT spherulites. Accordingly, the FETs with higher GB densities showed much poorer electrical characteristics than devices with lower GB density. Especially, GBs provide charge trapping sites which are responsible for bias-stress driven electrical instability. Dielectric surface treatment with a polystyrene brush layer clarified the GB-induced charge trapping by reducing charge trapping at the semiconductor-dielectric interface. Our study provides an understanding on GB induced bias instability for the development of high performance OFETs.

Investigation of High Current Tetracene-TFT Using Surface Nitrided SiO2 Gate Insulator Film

The use of surface nitrided SiO2 film as gate insulator of tetracene-TFT (Thin Film Transistor) has been proposed. Using Ar/N2 plasma, the nitridation has been carried out on the SiO2 surface to remove carrier trapping sites due to hydroxyl groups. As a result, transistor output characteristics have been drastically improved with extremely high current level using tetracene film as organic semiconductor material. Recently, there has been widely interested in organic-TFT because of its flexibility, ability to have a lot of material designs, applicability to large area devices and so on. However, the surface of conventional gate insulator such as SiO2and other metal oxide films often contain charge trapping sites due to the existence of hydroxyl (-OH) groups and surface defects. The carriers of organic-TFT have to move at the surface layer in the organic film adjacent to the gate insulator. Therefore it is important to control the surface and/or interface of organic film and gate insulator to avoid the carrier scattering at the charge trapping sites. Now, commonly used method to overcome this problem is deposition of SAM (Self-Assembled-Monolayer) film on the gate insulator. As a result, it is reported that electrical characteristics have been drastically improved. But it takes time about at least half a day to deposit the SAM film. In this paper, we have attempted to improve the carrier mobility in the tetracene film as organic semiconductor material, with surface nitride SiO2 film as the gate insulator for a short processing time. Figure1 shows transistor output characteristics with the channel length (L) = 70[um] and channel width (W) = 2000[um], respectively. It is clearly shown the extremely high current have been achieved from the tetracene-TFT on surface nitrided SiO2. On the contrary, no modulation due to gate bias could be achieved on SiO2film without the nitridation. Also, to clarify the difference, the property of tetracene/SiO2 interface of each sample, C-V measurement has been carried out. After the nitridation have been done on the SiO2 surface that had been etched with dil-HF to make hydroxyl groups, the width of C-V hysteresis is decreased. Therefore we can conclude the surface nitridation of SiO2 films with Ar/N2 plasma is effective method to remove charge trapping sites related to hydroxyl groups and improve transistor output characteristics. Figure 1

Nonvolatile Memory Characteristics of CdS Embedded Zr-Doped HfO2 High-k Dielectric MOS Capacitors

The nanocrystals embedded high dielectric constant (high-k) stack is a potential gate dielectric structure to replace the conventional poly-Si floating gate structure in nonvolatile memories (NVMs) for advantages of the low leakage current and improved reliability [1]. Several kinds of materials, such as ITO, ZnO, RuO, and CdSe, have been embedded in high-k dielectrics to attain large memory functions and long charge retention times [2,3]. CdS is another favorable material as the embedded layer for its n-type semiconductor attribute and large electron affinity of 4.3 eV [4]. The Zr-doped HfO2 (ZrHfO) high-k film has excellent bulk and interface properties, e.g., higher crystallization temperature, larger effective k value, and fewer interface states [2]. In this paper, authors investigated the capacitance-voltage (C-V) characteristics of the CdS embedded ZrHfO MOS capacitors.The ZrHfO/CdS/ZrHfO trilayer stack was deposited on the dilute HF cleaned p-type Si (100) wafer in one pumpdown with breaking the vacuum. The CdS layer was deposited from the CdS target in pure Ar at 5 mTorr and 60 W for 3 or 5 min between the sputter deposition of the tunnel and control ZrHfO layers. The post deposition annealing (PDA) was done at 900oC for 3 min under N2 atmosphere. The detailed device fabrication condition is the same as that described in Ref. 3. Previously, it was reported that the embedded CdSe layer was converted into discrete nanocrystals after the same PDA [2,3]. Therefore, CdS in this study may exist in the nanocrystalline form. However, further verification is required. Figure 1 shows the C-V hysteresis curves of the control and CdS embedded samples measured from -4 V to +4 V to -4 V at 1 MHz. Table 1 summarizes parameters calculated from Fig. 1, i.e., capacitance at the accumulation state (C), interface density of states (Dit ), equivalent oxide thickness (EOT), flat band voltage and shift (VFB and ¢VFB ), and charge trapping densities (Q ot). The C increases from 3.90×10-11 F for the control sample to 5.25×10-11 F for the CdS (3min) sample and 5.41×10-11 F for the CdS (5min) sample, which corresponds to the decrease of EOT. This is because the embedded CdS layer can reduce the diffusion of O2 to the ZrHfO/Si interface by the oxidization of CdS [5], which reduces the thickness of the interface layer and consequently increases the effective capacitance. On the other hand, since less O2 can reach the ZrHfO/Si interface, fewer Si dangling bonds are passivated and the higher interface density of states is detected. Then, the Dit increases, i.e., 4.67×1010 cm-2∙eV-1 for the control sample vs 2.45×1011 cm-2∙eV-1 for the CdS (3min) sample and 4.77×1011 cm-2∙eV-1 for the CdS (5min) sample. The control sample shows a very small memory window of 0.049 V, which suggests the few charge trapping sites in the bulk ZrHfO and ZrHfO/Si interface layers. However, when the CdS layer is embedded, the C-V hysteresis window and Qot increase dramatically, e.g., 0.404 V and 2.04×1012 cm-2 for CdS 3 min embedded sample and 0.498 V and 2.59×1012 cm-2 for CdS 5 min embedded sample.Figure 2 shows the C-V curves of the CdS embedded samples measured from -2 V to +1 V at 1 MHz before or after being stressed at Vg =-4 or +4 V for different times. Compared with the fresh sample, the C-V curves of both samples after being stressed at +4 V for 100 s have negligible small shifts, which indicates that the CdS embedded samples have very poor electron trapping capabilities. Nevertheless, after being stressed at -4 V, the C-V curve shifts towards the negative Vg direction due to the trapping of holes. This shift increases with the increase of stress time, i.e., from 0.12 V after 0.01 s stress to 0.38 V after 100 s stress for the CdS-3min sample and from 0.13 V after 0.01 s stress to 0.61 V after 100 s stress for the CdS-5min sample. Furthermore, because the more CdS is embedded in the high-k stack, the more charge trapping sites are created and the larger C-V curve shift is observed.[1] Y. Kuo, ECS Trans., 53, 121 (2013).[2] Y. Kuo, ECS Trans., 35, 13 (2011).[3] C.-C. Lin et al, JAP., 115, 084113 (2014).[4] A. Kanevce et al, IEEE J. Photovoltaics., 1, 99 (2011).[5] M. A. Islam et al, 38th IEEE PVSC, 000152 (2012). Figure 1

Nonvolatile Memory Characteristics of CdS Embedded Zr-Doped HfO2 High-k Dielectric MOS Capacitors

Nonvolatile memory device characteristics of the MOS capacitor containing the CdS embedded ZrHfO high-k gate dielectric layer have been investigated. The embedded CdS layer suppressed the growth of the high-k/Si interface layer and generated a large amount of charge trapping sites. The device preferred to trap holes under the negative voltage stress condition than electrons under the positive stress condition. The hole trapping density increased with the increase of stress time. The current density-voltage curve results confirmed the hole trapping mechanism and the quick release of shallow trapped holes upon the release of the stress voltage. More than 48% of the originally trapped charges remained in the devices after 10 years. The CdS embedded ZrHfO gate dielectric is a suitable structure for nonvolatile memories.

Investigation of High Current Tetracene-TFT Using Surface Nitrided SiO2 Gate Insulator Film

The use of surface nitrided SiO2 film as gate insulator of tetracene-TFT (Thin Film Transistor) has been proposed. Using Ar/N2 mixture gas plasma, the nitridation has been carried out on the SiO2 surface to remove charge-trapping sites due to hydroxyl groups. As a result, transistor output characteristics have been drastically improved with extremely high current level using tetracene film as organic semiconductor material. Also, to clarify the difference of the property of tetracene/SiO2 interface of each sample, C-V measurement has been carried out. After the nitridation have been done on the SiO2 surface that had been etched with dil-HF to make hydroxyl groups, the width of C-V hysteresis is decreased. Therefore we can conclude the surface nitridation of SiO2 films with Ar/N2 plasma are effective method to remove charge-trapping sites related to hydroxyl groups and improve transistor output characteristics.