Charge-trapping Flash Devices Research Articles

IGZO charge trap flash device for reconfigurable logic functions

We fabricated an indium gallium zinc oxide (IGZO) charge trap flash (CTF) device for logic-in-memory (LIM) applications. Initially, the nonvolatile memory characteristics of the IGZO CTF device were investigated under charge trapping and detrapping states in 104 s retention tests. Next, we constructed a common-source amplifier circuit containing the IGZO CTF device and demonstrated various input–output signal relationships by modulating the memory state of the device. Finally, we used interconnected IGZO CTF devices to demonstrate reconfigurable logic functions. Using series- and parallel-connected IGZO CTF devices, we developed 2-input NAND and 2-input NOR gates, respectively. Our experimental results showed that the IGZO CTF device is a promising future memory device and a tool for LIM technology.

Over- and Undercoordinated Atoms as a Source of Electron and Hole Traps in Amorphous Silicon Nitride (a-Si3N4).

Silicon nitride films are widely used as the charge storage layer of charge trap flash (CTF) devices due to their high charge trap densities. The nature of the charge trapping sites in these materials responsible for the memory effect in CTF devices is still unclear. Most prominently, the Si dangling bond or K-center has been identified as an amphoteric trap center. Nevertheless, experiments have shown that these dangling bonds only make up a small portion of the total density of electrical active defects, motivating the search for other charge trapping sites. Here, we use a machine-learned force field to create model structures of amorphous Si3N4 by simulating a melt-and-quench procedure with a molecular dynamics algorithm. Subsequently, we employ density functional theory in conjunction with a hybrid functional to investigate the structural properties and electronic states of our model structures. We show that electrons and holes can localize near over- and under-coordinated atoms, thereby introducing defect states in the band gap after structural relaxation. We analyze these trapping sites within a nonradiative multi-phonon model by calculating relaxation energies and thermodynamic charge transition levels. The resulting defect parameters are used to model the potential energy curves of the defect systems in different charge states and to extract the classical energy barrier for charge transfer. The high energy barriers for charge emission compared to the vanishing barriers for charge capture at the defect sites show that intrinsic electron traps can contribute to the memory effect in charge trap flash devices.

Operation Characteristics of Gate-All-Around Junctionless Flash Memory Devices With Si₃N₄/ZrO-Based Stacked Trapping Layer

The operation characteristics of polycrystalline Si (poly-Si) gate-all-around (GAA) junctionless (JL) charge-trapping (CT) flash memory devices with the Zr-based stacked trapping layer were studied in this work. Devices with the Si3N4/ZrO2 stacked trapping layer show enhanced erasing speeds and comparable retention characteristics in comparison to Si3N4/HfO2 due to many shallow energy traps and smaller valance band offset in the ZrO2 layer. By inserting Al2O3 between Si3N4 and ZrO2 trapping layer, the retention and endurance characteristics are improved. The erasing speed can be further improved by a Zr-rich oxide layer near the tunneling oxide since the energy barrier can confine more injected electrons near the tunneling oxide. The retention characteristic can be improved without sacrificing the erasing speed because some of the shallow traps can be passivated by NH3 plasma treatment on ZrO2. Hence, the ZrO-based stacked trapping layer is very promising for the poly-Si GAA JL CT flash devices for nonvolatile memory applications.

Modeling of program/erase transient in heterogeneous SiNx charge trap flash memories

Abstract Heterogeneous SiNx based charge trap flash (CTF) which has varying N/Si ratio ( x ) along the thickness of the charge-trapping layer (CTL) shows improved program/erase (P/E) transients. In this work, we present the P/E model invoking different nature of traps in N-rich and Si-rich CTL and investigate the physical processes behind the P/E improvement observed in heterogeneous CTF. A set of coupled equations that include Poisson's and rate equations for electrons and holes are solved considering the variation of CTL physical parameters along the thickness. The electron/hole injection current is accurately computed by including quantum effects at Si/SiO2 interface and taking into account the field-dependent relaxation of the energetic injected carriers. The simulation results of our model are in close agreement with the experimentally observed characteristics for five different sets of CTF devices with standard, Si-rich and N-rich homogeneous, and discretely and linearly graded heterogeneous CTF. Our study points out that the improvement in program transient for the heterogeneous CTF devices is attributed to the variation of trap density and trap energy along the CTL thickness and not due to lateral tunneling between the traps. The improvement in erase saturation and speed is due to high electron emission from the traps in Si-rich layer near bottom oxide of heterogeneous CTL.

Implementation of Boolean Logic Functions in Charge Trap Flash for In-Memory Computing

The use of nonvolatile arbitrary logic functions through emerging nonvolatile memory devices has been proposed to implement in-memory computing architecture. Here, in this paper, for the first time, we have proposed a nonvolatile stateful logic methodology based on a charge trap flash (CTF) memory device. Using multi-bit operation, functionally complete Boolean logic functions are experimentally demonstrated. The CTF devices exhibit perfect CMOS compatibility and excellent reliability as compared to other emerging memory devices. In addition, they do not require an additional select transistor, which leads to a more compact array configuration. Our CTF device and operation method may be a promising solution for the hardware implementation of non-von Neumann computing systems.

Operation characteristics of Poly-Si nanowire charge-trapping flash memory devices with SiGe and Ge buried channels

Operation characteristics of polycrystalline silicon (poly-Si) nanowire (NW) charge-trapping (CT) flash memory devices with a SiGe and a Ge buried channel are studied and compared in this work. The poly-Si NW devices with a Ge buried channel show faster programming and erasing speeds as compared to those with a SiGe one due to a lower energy barrier in tunneling layer with more Ge composition. The retention and endurance characteristics of devices with a Ge buried channel are similar to those with a SiGe one. Ge buried channel is promising to CT flash device for 3D nonvolatile memory applications.

Improving Memory Characteristics of Hydrogenated Nanocrystalline Silicon Germanium Nonvolatile Memory Devices by Controlling Germanium Contents.

Nonvolatile memory (NVM) with silicon dioxide/silicon nitride/silicon oxynitride (ONO(n)) charge trap structure is a promising flash memory technology duo that will fulfill process compatibility for system-on-panel displays, down-scaling cell size and low operation voltage. In this research, charge trap flash devices were fabricated with ONO(n) stack gate insulators and an active layer using hydrogenated nanocrystalline silicon germanium (nc-SiGe:H) films at a low temperature. In this study, the effect of the interface trap density on the performance of devices, including memory window and retention, was investigated. The electrical characteristics of NVM devices were studied controlling Ge content from 0% to 28% in the nc-SiGe:H channel layer. The optimal Ge content in the channel layer was found to be around 16%. For nc-SiGe:H NVM with 16% Ge content, the memory window was 3.13 V and the retention data exceeded 77% after 10 years under the programming condition of 15 V for 1 msec. This showed that the memory window increased by 42% and the retention increased by 12% compared to the nc-Si:H NVM that does not contain Ge. However, when the Ge content was more than 16%, the memory window and retention property decreased. Finally, this research showed that the Ge content has an effect on the interface trap density and this enabled us to determine the optimal Ge content.

Enhanced Programming and Erasing Speeds of Charge-Trapping Flash Memory Device With Ge Channel

Charge-trapping (CT) flash memory devices with Ge channel are studied for the first time. The operation characteristics of Ge-channel devices with different interfacial layers (IL), including GeO2, GeON, and AlON, are investigated. The programming/erasing speeds of devices with Ge channel can be significantly improved as compared with those with Si or SiGe channel. The retention properties of Ge-channel CT flash devices are much enhanced with a stacked tunneling layer formed by the low-temperature processes. However, the endurance characteristics of Ge-channel devices need improvement as compared with those of Si-channel devices. This may be resolved by a high-quality IL formed with an electron cyclotron resonance system and passivated with a H2 treatment.

Enhanced Operation Characteristics in Poly-Si Nanowire Charge-Trapping Flash Memory Device With SiGe Buried Channel

Operation characteristics in a polycrystalline silicon (poly-Si) nanowire (NW) charge-trapping (CT) flash memory device are studied with SiGe buried channel for the first time. Compared with the flash device with a general poly-Si NW channel, the device with SiGe buried channel shows improved programming and erasing speeds since the enhanced electric field in tunneling layer is enhanced by SiGe buried layer. The endurance characteristics are also improved by the SiGe buried channel while retention performances are retained. The SiGe buried channel is promising to CT flash device for 3D nonvolatile memory applications.

Threshold voltage instability mechanisms of nitride based charge trap flash memory--a review.

Technological scaling of charge trap device has become significantly more challenging due to two major physical limits revealed by International Technology Roadmap for Semiconductors (ITRS) 2011, i.e., (1) neighboring bit interference due to consistent shrinking in design floor space; (2) balancing act of ensuring sufficient number of electrons in shrinking storage layer to maintain stable threshold voltage (V(t)) against various V(t) instability mechanisms. Nitride based charge trap flash (CTF) is one of the better candidates to replace floating gate (FG) flash as the mainstream flash memory technology due to its inherent immunity to point defects and better device scalability. However, post cycled V(t) instability in the form of V(t) distribution shift and broadening of programmed/erased cells is still genuine reliability concerns for nitride based CTF devices. This is because the shift and broadening of V(t) distribution could degrade the operating window and thus caused premature failures of the devices. V(t) instability of nitride based CTF memory inevitably introduces statistical fluctuations in V(t) distribution of nitride based CTF which is detrimental to its long-term data retention performance. The scope of this review paper focuses on critical reliability challenges of future development of nitride based CTF development with emphasis on cell level V(t) instability mechanisms. Our review on recent findings of V(t) instability mechanisms are useful references for future development of nitride based CTF devices.

Improved programming/erasing speed of charge-trapping flash device with tunneling layer formed by low temperature nitrogen-rich SiN/SiO2 stack

For better performance on charge-trapping (CT) flash device, tunneling layer stacks of nitrogen (N)-rich SiN/SiO2 and low temperature (LT) N-rich SiN/SiO2 are studied. The programming and erasing speeds of CT flash device are significantly improved by the tunneling layer stacks due to the lower conduction and valence band offsets of N-rich and LT N-rich SiN, but worse retention is observed with the lower offsets. The effects of tunneling layer stacks on devices with silicon (Si)-rich SiN trapping layer are also studied. The programming and erasing speeds can be both improved due to its smaller bandgap. When stacked tunneling layers are applied to devices with Si-rich SiN trapping layer, their programming speeds are almost the same as those of devices with single tunneling layer. Only erasing speeds are improved by tunneling layer stacks. The retention properties of CT flash devices with Si-rich SiN trapping layer are not as good as those with standard one.

Graphene Gate Electrode for MOS Structure-Based Electronic Devices

We demonstrate that the use of a monolayer graphene as a gate electrode on top of a high-κ gate dielectric eliminates mechanical-stress-induced-gate dielectric degradation, resulting in a quantum leap of gate dielectric reliability. The high work function of hole-doped graphene also helps reduce the quantum mechanical tunneling current from the gate electrode. This concept is applied to nonvolatile Flash memory devices, whose performance is critically affected by the quality of the gate dielectric. Charge-trap flash (CTF) memory with a graphene gate electrode shows superior data retention and program/erase performance that current CTF devices cannot achieve. The findings of this study can lead to new applications of graphene, not only for Flash memory devices but also for other high-performance and mass-producible electronic devices based on MOS structure which is the mainstream of the electronic device industry.

Arsenic-Implanted HfON Charge-Trapping Flash Memory With Large Memory Window and Good Retention

We have fabricated the TaN-[SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> -LaAlO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> ]-HfON-[LaAlO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> -SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ]-Si charge-trapping Flash device. A large 6.4-V initial memory window, a 4.3-V 10-year extrapolated reten tion window at 125°C, and a 5.5-V endurance window at 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sup> cycles were measured under very fast 100-μs and low ±16-V program/erase. These excellent results were achieved using an As <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> implant into the HfON trapping layer, which were sig nificantly better than those of the control device without ion implantation.

Highly scaled charge-trapping layer of ZrON nonvolatile memory device with good retention

We have fabricated the TaN–[SiO2–LaAlO3]–ZrON–[LaAlO3–SiO2]–Si charge-trapping flash device with highly scaled 3.6 nm equivalent-Si3N4-thickness. This device shows large 4.9 V initial memory window, and good retention of 3.4 V ten-year extrapolated retention window at 85 °C, under very fast 100 μs and low ±16 V program/erase. These excellent results were achieved using deep traps formed in ZrON trapping layer by As+ implantation that was significantly better than those of control device without ion implantation.

Improvement on programming and erasing speeds for charge-trapping flash memory device with SiGe buried channel

SiGe buried channel with different Ge contents and various thicknesses of Si-cap layer on operating characteristics of charge-trapping (CT) flash devices were studied in this work. The results show that the programming and erasing speeds of CT flash devices are significantly improved by employing SiGe buried channel. Enhancement up to merely 20 times on programming speed was achieved. The retention characteristics of flash devices are satisfactory with suitable Ge content in SiGe buried channel and thickness of Si-cap layer. From the measurement of secondary ion mass spectroscopy, the operation characteristics of flash devices with SiGe channel were sensitive to the distribution of Ge atoms.

Barrier engineering in metal–aluminum oxide–nitride–oxide–silicon (MANOS) flash memory: Invited

The non-volatile memory market, especially the NAND market, has grown explosively in recent years and its business/market volume has become comparable to that of DRAM. NAND device technology has become a technology driver in physical dimension scaling because its structure and layout are simpler than DRAM and logic circuit. However, the current floating gate-type structure has inherent limiting factors in physical scaling. To overcome the scaling limit of floating gate NAND structures, a charge trap flash (CTF)-based structure is believed to show promise even though it still has issues, such as data retention and slow program erase, due to its unique gate stack structure. To improve erase speed and data retention, a barrier engineering (BE) approach for the tunneling layer and blocking layer/metal electrode shows promise for CTF devices. For the gate electrode, a stable, high WF solution is required. The large conduction band offset is necessary for the blocking oxide layer for better retention, but needs to be optimized in a sense of programming/erasing and retention. For the tunnel barrier, a high- k based tunnel barrier is a promising approach to improving erase speed and retention. However, reliability of tunnel oxide should be carefully studied. To determine the optimum gate stack for MANOS in terms of retention, P/E speed, and endurance, strategic approaches to improve device characteristics are required.

Improved Device Characteristics in Charge-Trapping-Engineered Flash Memory Using High-k Dielectrics

The much shallower trap energy in Si3N4 of [poly-Si]-SiO2-Si3N4-SiO2-Si (SONOS) charge-trapping flash (CTF) device than conventional poly-Si floating gate flash is the fundamental challenge for CTF device. We have pioneered the high-k trapping layer CTF memory to increase the trapping energy, where the AlGaN has a large conduction band offset to barrier oxide layer close to conventional poly-Si floating gate. Further device performance improvement is achieved using the novel Charge-Trapping-Engineered Flash (CTEF) device with double barriers for carrier confinements and double shallow-/deep-trapping layers for charge storage. Excellent memory device integrities of large extrapolated 10-year retention of 3.8 V at 150oC, 4 logic levels MLC operation, very fast 100 us write speed and good 100,000 cycling stress are measured at the same time. These excellent results may allow further down-scaling the flash memory for additional nodes.

Optical capacitance-voltage characterization of charge traps in the trapping nitride layer of charge trapped flash memory devices

Extracting the trap distribution in charge trapping layers of charge trap flash memory devices, an optical C-V method (OCVM) is proposed. Applying photons with λ=532nm to the oxide-nitride-oxide layer with 50∕60∕23Å in metal-oxide-nitride-oxide-semiconductor charge trap flash devices, the trap density in the charge trapping nitride layer is extracted to be 1.16×1018–1.67×1019cm−3eV−1 over the energy EC−Et=1.36–1.64eV. Combining sub-band-gap photons in C-V characterization, the OCVM method is free from the thermal and electrical stresses which are inherent in conventional characterization methods even though they are critical error factors for accurate characterization of charge trapped flash memory devices.

High Work-Function Metal Gate and High-&amp;lt;tex&amp;gt;$kappa$&amp;lt;/tex&amp;gt;Dielectrics for Charge Trap Flash Memory Device Applications

We report the impact of high work-function (/spl Phi//sub M/) metal gate and high-/spl kappa/ dielectrics on memory properties of NAND-type charge trap Flash (CTF) memory devices. In this paper, theoretical and experimental studies show that high /spl Phi//sub M/ gate and high permittivity (high-/spl kappa/) dielectrics play a key role in eliminating electron back tunneling though the blocking dielectric during the erase operation. Techniques to improve erase efficiency of CTF memory devices with a fixed metal gate by employing various chemicals and structures are introduced and those mechanisms are discussed. Though process optimization of high /spl Phi//sub M/ gate and high-/spl kappa/ materials, enhanced CTF device characteristics such as high speed, large memory window, and good reliability characteristics of the CTF devices are obtained.