Charge Redistribution Successive Approximation Research Articles

Analysis and Background Self-Calibration of Comparator Offset in Loop-Unrolled SAR ADCs

In conventional charge redistribution successive approximation register (SAR) ADCs that use a single comparator, the comparator offset causes no distortion but a dc shift in the transfer curve. In loop-unrolled (LU) SAR ADCs, on the other hand, mismatched comparator offset voltages introduce input-level-dependent errors to the conversion result, which deteriorates the linearity and limits the resolution. Still, the literature lacks a quantitative analysis on this phenomenon, and the resolution of most reported SAR ADCs of this kind, until recently, has been limited to 6 bit. In this paper, we analyze the effects of comparator offset voltage mismatch in LU-SAR ADCs, and establish the quantitative relation between individual offsets and the signal-to-noise-and-distortion ratio (SNDR) and the effective-number-of-bits. A statistical linearity model is proposed for yield estimation. Finally, an on-line deterministic calibration technique for auto-zeroing dynamic comparator offset is presented to treat the offsets mismatch and improve linearity. A 150-MS/s 8-bit LU-SAR ADC is fabricated in a 130-nm CMOS technology to validate the concept. The measured result shows that the calibration improves the SNDR from 33.7 to 42.9 dB. The ADC consumes $640~\mu \text{W}$ from a 1.2-V supply with a figure-of-merit of 37.5 fJ/conv-step.

An Ultra-Low Power Charge Redistribution Successive Approximation Register A/D Converter for Biomedical Applications.

Power consumption is one of the key design constraints in biomedical devices such as pacemakers that are powered by small non rechargeable batteries over their entire life time. In these systems, Analog to Digital Convertors (ADCs) are used as interface between analog world and digital domain and play a key role. In this paper we present the design of an 8-bit Charge Redistribution Successive Approximation Register (CR-SAR) analog to digital converter in standard TSMC 0.18μm CMOS technology for low power and low data rate devices such as pacemakers. The 8-bit optimized CR-SAR ADC achieves low power of less than 250nW with conversion rate of 1KB/s. This ADC achieves integral nonlinearity (INL) and differential nonlinearity (DNL) less than 0.22 least significant bit (LSB) and less than 0.04 LSB respectively as compared to the standard requirement for the INL and DNL errors to be less than 0.5 LSB. The designed ADC operates at 1V supply voltage converting input ranging from 0V to 250mV.

An NTF-enhanced incremental ΣΔ modulator using a SAR quantizer

In this paper, a noise transfer function (NTF) enhanced incremental sigma-delta (ΣΔ) modulator is presented. It employs a charge redistribution successive approximation register (SAR) analog-to-digital converter (ADC) in an error-feedback scheme to achieve an extra noise-shaping order. Using a multi-bit SAR quantizer not only improves the stability and power consumption but also facilitates the realization of both the adder situated in front of the quantizer and the whole error-feedback loop. As a design example, a multiplexed 2nd-order modulator based on the proposed architecture is simulated in TSMC 90nm CMOS technology using Spectre with a 1V single power supply. The simulation results show a signal-to-noise and distortion ratio (SNDR) of 85.3dB within a signal bandwidth of 20kHz (1kHz/channel) at 5MHz sampling frequency. The power consumption for each channel is 8.6µW.

A 10 bit 16-to-26 MS/s flexible window SAR ADC for digitally controlled DC–DC converters in 28 nm CMOS

This paper presents a 10 bit charge redistribution successive approximation analog-to-digital converter (ADC) for integrated digitally controlled DC---DC converters. A timing efficient implementation of a window function is proposed, where only a reduced input range is converted. A redundant search is applied to overcome the speed limitation of the analog components. The window mode enables further speed enhancement without an increase of clock frequency and power consumption. Position of the set-point and size of the window is digitally adjustable every conversion. Fabricated in 28 nm low-power CMOS technology the ADC occupies only 110 × 85 µm2. In full range mode a conversion rate of 16 MS/s is achieved and in window mode 26.7 MS/s, respectively. With a measured total power consumption of 710 µW and 9.1 bit ENOB a FOM of 81 fJ/conv-step is reached. A large input range with constant resolution, highly linear characteristic, and high robustness to PVT variations together make this ADC an advantageous alternative to delay line or ring oscillator based window ADCs. The highly digital nature of the proposed architecture allows implementation in modern sub-100 nm CMOS technologies.

Passive reference-sharing SAR ADC

Charge-redistribution successive approximation register (SAR) analog-to-digital converters (ADCs) are widely used for their simple architecture, inherent low-power consumption and small footprint. Several techniques aiming to reduce the power consumption, to increase the speed, and to reduce the capacitance spread have been developed, such as splitting the digital-to-analog converter (DAC) capacitor array, and charging and discharging the DAC capacitors in multiple steps. In this paper, a fully differential, low-power, passive reference voltage sharing SAR ADC architecture is presented, along with its theoretical analysis and test results. In this architecture, suitable for low sampling rate and low-resolution applications, the reference voltage is scaled down by successively connecting equally sized capacitors in parallel, allowing the use of small capacitor for its implementation. The implemented 6-bit ADC is one of the smallest ADCs reported in a 180-nm technology, and features a FoM between 30.8 and 39.3fJ per conversion step without considering the clock generator power consumption.

An error-feedback noise-shaping SAR ADC in 90 nm CMOS

In this paper, a new structure is proposed to utilize the noise-shaping in a charge redistribution successive approximation register (SAR) analog-to-digital converter (ADC). The proposed ADC is bas...

A 90-MS/s 11-MHz-Bandwidth 62-dB SNDR Noise-Shaping SAR ADC

Although charge-redistribution successive approximation (SAR) ADCs are highly efficient, comparator noise and other effects limit the most efficient operation to below 10-b ENOB. This work introduces an oversampling, noise-shaping SAR ADC architecture that achieves 10-b ENOB with an 8-b SAR DAC array. A noise-shaping scheme shapes both comparator noise and quantization noise, thereby decoupling comparator noise from ADC performance. The loop filter is comprised of a cascade of a two-tap charge-domain FIR filter and an integrator to achieve good noise shaping even with a low-quality integrator. The prototype ADC is fabricated in 65-nm CMOS and occupies a core area of 0.03 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Operating at 90 MS/s, it consumes 806 μW from a 1.2-V supply.

Statistical Analysis of ENOB and Yield in Binary Weighted ADCs and DACS With Random Element Mismatch

Mismatch motivates many of the design decisions for binary weighted, ratiometric converters, such as successive approximation (SAR) analog-to-digital converters (ADC), but the statistical relationship between mismatch and signal-to-noise-plus-distortion ratio (SNDR) has not been precisely quantified. In this paper, we analyze the effects of capacitor mismatch in a binary weighted, charge redistribution SAR ADC and derive a new analytic expression relating capacitor mismatch and the effective-number-of-bits (ENOB). We then explore the statistics of this new expression and develop a model that accurately predicts yield in terms of ENOB. Finally, the major results of this paper are generalized into a simple and compact design equation that relates resolution, mismatch, and ENOB to yield for all binary weighted, ratiometric converters. The expressions derived in this paper offer practical insight into the relationship between mismatch and performance for all binary, weighted ratiometric converters with these results validated through numerical simulations.