A 90-MS/s 11-MHz-Bandwidth 62-dB SNDR Noise-Shaping SAR ADC

Abstract

Although charge-redistribution successive approximation (SAR) ADCs are highly efficient, comparator noise and other effects limit the most efficient operation to below 10-b ENOB. This work introduces an oversampling, noise-shaping SAR ADC architecture that achieves 10-b ENOB with an 8-b SAR DAC array. A noise-shaping scheme shapes both comparator noise and quantization noise, thereby decoupling comparator noise from ADC performance. The loop filter is comprised of a cascade of a two-tap charge-domain FIR filter and an integrator to achieve good noise shaping even with a low-quality integrator. The prototype ADC is fabricated in 65-nm CMOS and occupies a core area of 0.03 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Operating at 90 MS/s, it consumes 806 μW from a 1.2-V supply.