Charge Redistribution Successive Approximation Register Research Articles

A passive and low-complexity Compressed Sensing architecture based on a charge-redistribution SAR ADC

An innovative analog-to-digital converter (ADC) architecture is proposed, with the aim of acquiring an input signal according to the Compressed Sensing (CS) paradigm and without the need for dedicated active analog blocks. Its core is the capacitive array employed in traditional successive-approximation-register (SAR) ADCs. Introducing only a few additional switches, the array can compute the linear combination of consecutive signal samples, as required by the CS encoding.To manage the presence of leakage currents, which may impair signal reconstruction, a compensation circuit is considered, allowing close-to-ideal performance of the system when properly designed. A neural network-based decoding strategy is also analyzed, with up to 20 dB of additional reconstruction quality with respect to standard algorithms. Synthetic electrocardiogram signals are used to validate optimizations both at the hardware level in the encoding block and at the software level in the decoder.

A data-dependent energy reduction algorithm for SAR ADC using self-adaptive window

A new data-dependent energy reduction algorithm for successive approximation register (SAR) analog-to-digital convert (ADC) is presented in this paper. The proposed algorithm starts with a less significant bit (LSB) window with N-bit length, which is configurable depending on signal characteristics. By using less significant bit to more significant bit (L2M) successive extending (SE), the signal window is self-adaptive to cover the input signal within boundary. The proposed technique leads to less mean bit trials per sample, suggesting higher energy efficiency in many data-dependant ADC applications. Furthermore, this algorithm can be implemented based on conventional charge redistribution SAR ADC without any change in analog circuits. According to MATLAB simulation, the proposed technique is able to reduce mean bit trials effectively in biomedical signal detection applications. The simulation results show 37.9%, 32.3% and 18.2% less mean bit trials than using conventional SAR algorithm in processing electrocardiogram (ECG), electroencephalogram (EEG) and in electro-myography (EMG) signals respectively.

A 10-b 20-MS/s SAR ADC With DAC-Compensated Discrete-Time Reference Driver

Successive approximation register (SAR) analogto-digital converters (ADCs) with a charge-redistribution (CR) digital-to-analog converter (DAC) usually require a power-hungry reference driver or large decoupling capacitance, occupying significant chip area. This paper presents a CR SAR ADC with an integrated low-power and area-efficient discrete-time reference driver. An on-chip capacitor is pre-charged to the reference voltage during the tracking phase and drives the DAC of the SAR ADC passively during the conversion phase. The charge sharing between the driving capacitor and the DAC will cause reference voltage drop and code-dependent non-binary DAC switching steps. This is compensated by switching an auxiliary DAC array together with the regular binary DAC array according to each specific code. The compensation relaxes the required decoupling capacitor and introduces little overhead in power or chip area. The above-mentioned driving scheme is applied to a 10-b 20-MS/s successive approximation register (SAR) ADC fabricated in 65-nm CMOS, where the first three DAC switching steps are compensated. Moreover, redundancy is utilized to reduce the impact of reference voltage drop further. With a near-Nyquist input tone, the signal to noise and distortion ratio (SNDR) and spurious free dynamic range (SFDR) of the SAR ADC with the uncompensated reference driver are 54.4 and 58.9 dB, respectively. After enabling the compensation, the SNDR and SFDR are increased to 56.8 and 72.4 dB, achieving 2.4 and 13.5 dB improvement, respectively. The SAR ADC consumes a total power of 133.1 μW while the discrete-time reference driver with and without compensation add 17.2 and 14.0 μW, respectively. The SAR ADC with integrated reference driver occupies a chip area of 0.081 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> where 8.6% is occupied by the reference driver.

Analysis and Background Self-Calibration of Comparator Offset in Loop-Unrolled SAR ADCs

In conventional charge redistribution successive approximation register (SAR) ADCs that use a single comparator, the comparator offset causes no distortion but a dc shift in the transfer curve. In loop-unrolled (LU) SAR ADCs, on the other hand, mismatched comparator offset voltages introduce input-level-dependent errors to the conversion result, which deteriorates the linearity and limits the resolution. Still, the literature lacks a quantitative analysis on this phenomenon, and the resolution of most reported SAR ADCs of this kind, until recently, has been limited to 6 bit. In this paper, we analyze the effects of comparator offset voltage mismatch in LU-SAR ADCs, and establish the quantitative relation between individual offsets and the signal-to-noise-and-distortion ratio (SNDR) and the effective-number-of-bits. A statistical linearity model is proposed for yield estimation. Finally, an on-line deterministic calibration technique for auto-zeroing dynamic comparator offset is presented to treat the offsets mismatch and improve linearity. A 150-MS/s 8-bit LU-SAR ADC is fabricated in a 130-nm CMOS technology to validate the concept. The measured result shows that the calibration improves the SNDR from 33.7 to 42.9 dB. The ADC consumes $640~\mu \text{W}$ from a 1.2-V supply with a figure-of-merit of 37.5 fJ/conv-step.

Low-Power High-Linearity Switching Procedure for Charge-Redistribution SAR ADC

An energy-efficient capacitive switching scheme in successive approximation register (SAR) analogue-to-digital converter (ADC) is proposed for biomedical applications. With novel sequence initialization and by reducing the up-switching steps during the A/D conversion, the average switching energy of this proposed procedure is reduced by over 98.7% compared with the conventional architecture after taking the parasitic capacitance into consideration. The number of capacitors in the proposed capacitor array is just 1/4 of that in the conventional switching scheme. Moreover, behavioral simulation performed in MATLAB for the 10-bit SAR ADC shows that the linearity performance of this proposed switching scheme is much better than that of previous architectures.

An Ultra-Low Power Charge Redistribution Successive Approximation Register A/D Converter for Biomedical Applications.

Power consumption is one of the key design constraints in biomedical devices such as pacemakers that are powered by small non rechargeable batteries over their entire life time. In these systems, Analog to Digital Convertors (ADCs) are used as interface between analog world and digital domain and play a key role. In this paper we present the design of an 8-bit Charge Redistribution Successive Approximation Register (CR-SAR) analog to digital converter in standard TSMC 0.18μm CMOS technology for low power and low data rate devices such as pacemakers. The 8-bit optimized CR-SAR ADC achieves low power of less than 250nW with conversion rate of 1KB/s. This ADC achieves integral nonlinearity (INL) and differential nonlinearity (DNL) less than 0.22 least significant bit (LSB) and less than 0.04 LSB respectively as compared to the standard requirement for the INL and DNL errors to be less than 0.5 LSB. The designed ADC operates at 1V supply voltage converting input ranging from 0V to 250mV.

An NTF-enhanced incremental ΣΔ modulator using a SAR quantizer

In this paper, a noise transfer function (NTF) enhanced incremental sigma-delta (ΣΔ) modulator is presented. It employs a charge redistribution successive approximation register (SAR) analog-to-digital converter (ADC) in an error-feedback scheme to achieve an extra noise-shaping order. Using a multi-bit SAR quantizer not only improves the stability and power consumption but also facilitates the realization of both the adder situated in front of the quantizer and the whole error-feedback loop. As a design example, a multiplexed 2nd-order modulator based on the proposed architecture is simulated in TSMC 90nm CMOS technology using Spectre with a 1V single power supply. The simulation results show a signal-to-noise and distortion ratio (SNDR) of 85.3dB within a signal bandwidth of 20kHz (1kHz/channel) at 5MHz sampling frequency. The power consumption for each channel is 8.6µW.

Passive reference-sharing SAR ADC

Charge-redistribution successive approximation register (SAR) analog-to-digital converters (ADCs) are widely used for their simple architecture, inherent low-power consumption and small footprint. Several techniques aiming to reduce the power consumption, to increase the speed, and to reduce the capacitance spread have been developed, such as splitting the digital-to-analog converter (DAC) capacitor array, and charging and discharging the DAC capacitors in multiple steps. In this paper, a fully differential, low-power, passive reference voltage sharing SAR ADC architecture is presented, along with its theoretical analysis and test results. In this architecture, suitable for low sampling rate and low-resolution applications, the reference voltage is scaled down by successively connecting equally sized capacitors in parallel, allowing the use of small capacitor for its implementation. The implemented 6-bit ADC is one of the smallest ADCs reported in a 180-nm technology, and features a FoM between 30.8 and 39.3fJ per conversion step without considering the clock generator power consumption.

An error-feedback noise-shaping SAR ADC in 90 nm CMOS

In this paper, a new structure is proposed to utilize the noise-shaping in a charge redistribution successive approximation register (SAR) analog-to-digital converter (ADC). The proposed ADC is bas...

The Impact of Noise and Mismatch on SAR ADCs and a Calibratable Capacitance Array Based Approach for High Resolutions

Abstract This paper describes widely used capacitor structures for charge-redistribution (CR) successive approximation register (SAR) based analog-to-digital converters (ADCs) and analyzes their linearity limitations due to kT/C noise, mismatch and parasitics. Results of mathematical considerations and statistical simulations are presented which show that most widespread dimensioning rules are overcritical. For high-resolution CR SAR ADCs in current CMOS technologies, matching of the capacitors, influenced by local mismatch and parasitics, is a limiting factor. For high-resolution medium-speed CR SAR ADCs, a novel capacitance array based approach using in-field calibration is proposed. This architecture promises a high resolution with small unit capacitances and without expensive factory calibration as laser trimming.