In this paper, we present the performance comparison of a planar dual-gate semiconducting-nanotube thin-film transistor (SNTFT) with single-gate SNTFTs. A thin film of 95% enriched semiconducting single-walled carbon nanotubes (SWCNTs) is deposited on the amino-silane-modified hafnium oxide (HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> ) surface. HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> deposited by radio-frequency sputtering is used as the dielectric material for the back gate of the SNTFT, and SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> is used as the dielectric material for the top gate. The performance of SNTFTs with the gate structures located at the top, bottom, or both the top and the bottom (dual gate) of the SWCNT thin-film channel is compared. All SNTFTs have exhibited a p-type output characteristic behavior with distinct saturation and a linear region of operation. The electrical characterization of these devices shows that the dual-gate SNTFT out performs the single-gate devices in terms of subthreshold slopes, threshold voltage, and on-off current ratios. The dual-gate SNTFT exhibits a subthreshold slope of 280 mV/dec, a threshold voltage of -0.65 V, and a maximum on-off drain current ratio of 1.2 × 103. A maximum transconductance value of 5.89 μS and a charge carrier mobility value of 2.26 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /V · s obtained for the dual-gate SNTFT are greater compared with the corresponding values of single-gate SNTFTs having identical dimensions.