Characteristics Of Flash Memory Research Articles

플래시 메모리기반 저장장치에서 효율적 메타데이터 관리 기법

현재 NAND 플래시 메모리기반 저장장치는 NAND 플래시 메모리의 단점을 감추고 장점을 극대화해 나가며 그 활용 영역을 지속적으로 넓혀왔다. 특히, 이러한 저장장치는 NAND 플래시 메모리의 고유한 특성인 "쓰기 전 지우기" 특성을 감추기 위하여 내부적으로 플래시 변환 계층(Flash Translation Layer)이라 불리는 소프트웨어 계층을 포함하고 있다. 플래시 변환 계층은 호스트로부터 요청된 데이터를 관리하기 위한 메타데이터를 포함하며, 메타데이터는 호스트의 요청들을 처리하기 위해 자주 접근되는 데이터이므로 내부 메모리에 저장되어 관리된다. 따라서 메모리에 저장된 메타데이터는 전원손실이 발생하게 되는 경우 모두 소멸되므로, 메타데이터를 주기적으로 저장하고 초기화 과정을 통해 메타데이터를 메모리에 적재할 수 있는 메타데이터 관리 정책이 필요하다. 따라서 우리는 메타데이터 관리의 핵심 요구사항을 모두 만족하면서 효율적으로 동작하는 메타데이터 관리 정책을 제안하며, 실험을 통해 제안하는 기법의 효율성을 증명하였다. Recently, NAND flash based storage devices are being used as a storage device in various fields through hiding the limitations of NAND flash memory and maximizing the advantages. In particular, those storage devices contain a software layer called Flash Translation Layer(FTL) to hide the "erase-before-write" characteristics of NAND flash memory. FTL includes the metadata for managing the data requested from host. That metadata is stored in internal memory because metadata is very frequently accessed data for processing the requests from host. Thus, if the power-loss occurs, all data in memory is lost. So metadata management scheme is necessary to store the metadata periodically and to load the metadata in the initialization step. Therefore we proposed the scheme which satisfies the core requirements for metadata management and efficient operation. And we verified the efficiency of proposed scheme by experiments.

An Efficient Flash Translation Layer for Large Block NAND Flash Devices

Recently, flash memory is widely used as a non-volatile storage for embedded applications such as smart phones, MP3 players, digital cameras and so on. The software layer called flash translation layer (FTL) becomes more important since it is a key factor in the overall flash memory system performance. Many researchers have proposed FTL algorithms for small block flash memory in which the size of a physical page of flash memory is equivalent to the size of a data sector of the file system. However, major flash vendors have now produced large block flash memory in which the size of a physical page is larger than the file system's data sector size. Since large block flash memory has new features, designing FTL algorithms specialized to large block flash memory is a challenging issue. In this paper, we provide an efficient FTL named LSTAFF* for large block flash memory. LSTAFF* is designed to achieve better performance by using characteristics of large block flash memory and to provide safety by abiding by restrictions of large block flash memory. Experimental results show that LSTAFF* outperforms existing algorithms on a large block flash memory.

Effect of energy-band bending induced by precipitation of ZrO2 nanocrystals on memory characteristics of charge-trap flash memory

Charge-trap flash-memory capacitors incorporating Zr0.7Si0.3Ox and Zr0.6Si0.4Ox films as the charge-trapping layer were fabricated and investigated. The Zr0.7Si0.3Ox trapping layer exhibited a large memory window of 11.2 V, good retention characteristics, and a higher program/erase speed than the Zr0.6Si0.4Ox trapping layer. The remarkable improvement of the memory characteristics are attributed to the ZrO2 nanocrystals that precipitated from the Zr0.7Si0.3Ox matrix after the annealing treatment, inducing the redistribution of the elemental compositions and the energy-band bending. The results indicate that the bended-energy-band Zr0.7Si0.3Ox trapping layer is a promising candidate for future nonvolatile-memory applications.

Electrical degradation mechanisms of nanoscale charge trap flash memories due to trapped charge in the oxide layer

The deterioration of the electrical characteristics of charge trap flash (CTF) memories with a silicon-oxide-nitride-oxide-silicon (SONOS) structure due to the charge traps in the oxide layers attributed to the random trapping and detrapping processes was investigated. Simulation results for the CTF memories showed that the threshold voltage shift was decreased by the charge trapped in the oxide layers in the SONOS structure and that the charge trapped in the blocking oxide had more significant effects than that trapped in the tunneling oxide. The degradation effects of the charge trapped in the blocking oxide on the electrical characteristics of the CTF memories were clarified by examining the vertical electric field in the device.

TRIFL

Due to several important features, such as high performance, low power consumption, and shock resistance, NAND flash has become a very popular stable storage medium for embedded mobile devices, personal computers, and even enterprise servers. However, the peculiar characteristics of flash memory require redesigning the existing data storage and indexing techniques that were devised for magnetic hard disks. In this article, we propose TRIFL, an efficient and generic TRajectory Index for FLash. TRIFL is designed around the key requirements of trajectory indexing and flash storage. TRIFL is generic in the sense that it is efficient for both simple flash storage devices such as SD cards and more powerful devices such as solid state drives. In addition, TRIFL is supplied with an online self-tuning algorithm that allows adapting the index structure to the workload and the technical specifications of the flash storage device to maximize the index performance. Moreover, TRIFL achieves good performance with relatively low memory requirements, which makes the index appropriate for many application scenarios. The experimental evaluation shows that TRIFL outperforms the representative indexing methods on magnetic disks and flash disks.

The Storage Cell Circuit with Memristor Characteristics of Poly(N-Vinylcarbazole) Films**Supported by the China Postdoctoral Science Foundation under Grant No 2011M50070.

A kind of non-conjugated polymer memory material, poly(N-vinylcarbazole), is used to investigate silicon-based storage performance with the fact that the one-bit storage cell circuit consists of a sandwiched indium-tinoxide/poly(N-vinylcarbazole)/Al and an n-type metal-oxide-semiconductor field effect transistor. The memristor on the basis of a nano poly(N-vinylcarbazole) film exhibits electrical bistability and flash memory features, for which the switching-on voltage is −1 V and the on/off current ratio approaches 104. At ambient temperature, the memory circuit possesses higher reliability within the programming time 104 s. The output voltage is close to 0.5 V during logic 1, while it is approximately 14 mV in the logic 0. This paves the way for the study on the technology concerning the binary encoding and data storage of nonvolatile memories.

Electrical Characteristics of Charge Trap Flash Memory with a Composition Modulated (ZrO2)x(Al2O3)1-xFilm

This research proposes the use of a composition modulated (ZrO₂)_x(Al₂O₃)_1-x film as a charge trapping layer for charge trap flash memory; this is possible when the Zr (Al) atomic percent is controlled to form a variable bandgap as identified by the valence band offsets and electron energy loss spectrum measurements. Compared to memory devices with uniform compositional (ZrO₂)_0.1(Al₂O₃)_0.9 or a (ZrO₂)_0.92(Al₂O₃)_0.08 trapping layer, the memory device using the composition modulated (ZrO₂)_x(Al₂O₃)_1-x as the charge trapping layer exhibits a larger memory window (6.0 V) at the gate sweeping voltage of ±8 V, improved data retention, and significantly faster program/erase speed. Improvements of the memory characteristics are attributed to the special energy band alignments resulting from non-uniform distribution of elemental composition. These results indicate that the composition modulated (ZrO₂)_x(Al₂O₃)_1-x film is a promising candidate for future nonvolatile memory device applications.

Effective flash-based SSD caching for high performance home cloud server

In the home cloud environment, the storage performance of home cloud servers, which govern connected devices and provide resources with virtualization features, is critical to improve the end-user experience. To improve the storage performance of virtualized home cloud servers in a cost-effective manner, caching schemes using flash-based solid state drives (SSD) have been widely studied. Although previous studies successfully narrow the speed gap between memory and hard disk drives, they only focused on how to manage the cache space, but were less interested in how to use the cache space efficiently taking into account the characteristics of flash-based SSD. Moreover, SSD caching is used as a read-only cache due to two well-known limitations of SSD: slow write and limited lifespan. Since storage access in virtual machines is performed in a more complex and costly manner, the limitations of SSD affect more significantly the storage performance. This paper proposes a novel SSD caching scheme and virtual disk image format, named sequential virtual disk (SVD), for achieving high-performance home cloud environments. The proposed techniques are based on the workload characteristics, in which synchronous random writes dominate, while taking into consideration the characteristics of flash memory and storage stack of the virtualized systems. Unlike previous studies, SSD is used as a read-write cache in the proposed caching scheme to effectively mitigate the performance degradation of synchronous random writes. The prototype was evaluated with some realistic workloads, through which the developed scheme was shown to allow improvement of the storage access performance by 21% to 112%, with reduction in the number of erasures on SSD by about 56% on average.

Data Sorting in Flash Memory

Because flash memory now provides an economical solution for various portable devices and embedded systems, an NAND flash-based storage system has replaced the hard disk drive in many applications. Recently, the implementation of database systems using an NAND flash-based storage system has become an important research topic. In particular, the external sorting is an important operation in database systems. With the very distinctive characteristics of flash memory, the typical external sorting system that adopts a clustered sorting process can result in performance degradation and reduce the reliability of flash memory. In this article, we will propose an unclustered sorting method that considers the unique characteristics of flash memory, and we then propose a decision rule to exploit the advantages of both clustered and unclustered sorting. The decision rule can separate records according to their record length, sort them appropriately by the clustered and unclustered sorting, and merge the sorted results. The experimental results show that the proposed method can improve performance in an NAND flash-based storage system (i.e., solid-state drive).

Zombie Chasing: Efficient Flash Management Considering Dirty Data in the Buffer Cache

This paper presents a novel technique, called Zombie Chasing, for efficient flash management in solid state drives (SSDs). Due to the unique characteristics of NAND flash memory, SSDs need to accurately understand the liveness of the data stored in themselves. Recently, the TRIM command has been introduced to notify SSDs of dead data caused by file deletions, which otherwise could not be tracked by SSDs. This paper goes one step further and proposes a new liveness state, called the zombie state, to denote live data that will be dead shortly due to the corresponding dirty data in the buffer cache. We also devise new zombie-aware garbage collection algorithms which utilize the information about such zombie data inside SSDs. To evaluate Zombie Chasing, we implement zombie-aware garbage collection algorithms in the prototype SSD and modify the Linux kernel and the Oracle DBMS to deliver the information on the zombie data to the prototype SSD. Through comprehensive evaluations using our in-house micro-benchmark and the TPC-C benchmark, we observe that Zombie Chasing improves SSD performance effectively by reducing garbage collection overhead. Especially, our evaluation with the TPC-C benchmark on the Oracle DBMS shows that Zombie Chasing enhances the Transactions Per Second (TPS) value by up to 22% with negligible overhead.

Clustered page-level mapping for flash memory-based storage devices

Recent consumer devices such as smartphones, smart TVs and tablet PCs adopt NAND flash memory as storage device due to its advantages of small size, reliability, low power consumption, and high performance. The unique characteristics of NAND flash memory require an additional software layer, called flash translation layer (FTL), between traditional file systems and flash memory. In order to reduce the garbage collection cost, FTLs generally try to separate hot and cold data. Previous hot and cold separation techniques monitor the storage access patterns within storage device, or exploit file system hints from host system. This paper proposes a novel clustered page-level mapping, called CPM, which can separate hot and cold data efficiently by allocating different flash memory block groups to different logical address regions. CPM can reduce the FTL map loading overhead during garbage collection and it does not require any high-cost monitoring overhead or host hint. This paper also proposes a K-associative version of CPM, called K-CPM, which allows different logical address regions to share a physical block group in order to achieve high block utilizations. Experimental results show that CPM improves the storage I/O performance by about 54% compared with a previous page-level mapping FTL, and K-CPM further improves the performance by about 19.4% compared with CPM.

RFFE: A Buffer Cache Management Algorithm for Flash-Memory-Based SSD to Improve Write Performance

Flash-memory-based solid-state drives use multiple NAND flash memory chips as storage media and deploy a large-sized random access memory (RAM) inside it. This RAM buffer absorbs the read and write requests by file systems, and thus the resulting write requests to NAND flash memory are determined by the buffer replacement scheme. Many of the previously proposed algorithms concentrate on improving the random write performance by reordering the writes, addressing the temporal locality, or evicting the clean pages beforehand. However, the sequential write patterns in the incoming write stream are not completely utilized by the flash translation layer; this increases garbage collection overhead. To overcome this limitation, we propose a novel algorithm, called random first flash enlargement (RFFE), to improve the performance of the write operation. The algorithm identifies the interleaved sequential writes and builds various policy decisions, and the write sequence is constructed by contemplating the flash memory characteristics. In particular, the write stream is written into an appropriate log block area. Trace driven simulation is compared with the previously proposed least recently used fully-associative sector translation (FAST), block padding least recently used (BPLRU), and recently-evicted-first (REF) buffer management schemes. The result shows that the RFFE outperforms the previously proposed schemes with respect to merge, erase, and write count.

New Fullerene-Based Polymers and Their Electrical Memory Characteristics

Covalent incorporations into polymers of fullerene were achieved via the Cu(I)-catalyzed azide–alkyne click polymerizations of a fullerene derivative monomer functionalized with 5-(trimethylsilyl)pent-4-yn-1-yl groups and a comonomer functionalized with azidomethyl groups, producing the novel fullerene polymers P1-C60 and P2-C60. Despite their extremely high fullerene loading levels, the polymers were soluble in common organic solvents and exhibited no aggregation of fullerene units in films. Moreover, devices containing these fullerene polymers were easily fabricated with common coating processes that exhibit excellent unipolar and bipolar flash memory characteristics as well as unipolar permanent memory characteristics, with high ON/OFF current ratios, long retention times, and low power consumption. These electrical switching behaviors were favorably operated by electron injection. Overall, these devices are the first n-type bipolar and unipolar digital polymer memory devices which can be operated in flash and write-once-read-many-times modes.

Disturbance characteristics of charge trap flash memory with tunneling field-effect transistor

In this study, the disturbance characteristics of silicon–oxide–nitride–oxide–silicon (SONOS) memory based on the tunneling field-effect transistor (TFET) are investigated in terms of the Fowler–Nordheim (FN) program. Since the TFET SONOS memory uses a depletion channel region for program inhibition, the tunneling of an inhibited cell considers both the electron concentration and the vertical electric field. The effects of both parameters on tunneling current are analyzed using device simulation and the tunneling current equation. The tunneling current of the source-side region depends on the electric field and that of the drain-side region depends on the electron concentration. These results can be applied to the performance optimization of the TFET SONOS memory.

Page Replacement for Write References in NAND Flash Based Virtual Memory Systems

Contemporary embedded systems often use NAND flash memory instead of hard disks as their swap space of virtual memory. Since the read/write characteristics of NAND flash memory are very different from those of hard disks, an efficient page replacement algorithm is needed for this environment. Our analysis shows that temporal locality is dominant in virtual memory references but that is not the case for write references, when the read and write references are monitored separately. Based on this observation, we present a new page replacement algorithm that uses different strategies for read and write operations in predicting the re-reference likelihood of pages. For read operations, only temporal locality is used; but for write operations, both write frequency and temporal locality are used. The algorithm logically partitions the memory space into read and write areas to keep track of their reference patterns precisely, and then dynamically adjusts their size based on their reference patterns and I/O costs. Without requiring any external parameter to tune, the proposed algorithm outperforms CLOCK, CAR, and CFLRU by 20%–66%. It also supports optimized implementations for virtual memory systems.

Performance Evaluation of Flash Translation Layer Considering Utilization and Dynamic Over-provisioning

Flash translation layer (FTL) is a firmware embedded in NAND-based block devices. It hides unique characteristics of NAND flash memory and emulates a standard block device interface. The overall performance of NAND-based block devices is mainly determined by the efficiency of the FTL schemes, and thus, it is important to evaluate the FTL performance to design high-speed NAND-based block devices, which is a main objective of this work. Whereas most previous works have not considered device utilization from a FTL perspective and have fixed the over-provisioning factor, this work evaluates their performance varying device utilization and allows unused space to be used as over-provision area. A trace-driven simulation shows that device utilization significantly influences on FTL’s performance. Especially, the page mapping FTL is vulnerable against high utilization, even though it delivers a good performance at low utilization. In contrast, the fully associative sector translation (FAST) FTL is less sensitive to the utilization and delivers a competing performance. It even outperforms the page mapping FTL at high utilization.

Enhancement of electrical characteristics of the coupling ratio and the program/erase operation for NAND flash memories with an asymmetric interpoly-dielectric structure

The electrical characteristics of NAND flash memories with an asymmetric interpoly-dielectric (IPD) structure and a conventional IPD structure were simulated by using a technology computer-aided sentaurus simulation tool to enhance their device performance. The floating gate potential and the on-current level of the NAND memory devices with an asymmetric IPD structure were higher than those with a conventional IPD structure. The maximum electric field formed at the rounding boundary area of the floating gate and the blocking oxide layer in an asymmetric IPD structure was 34% smaller than that in a conventional IPD structure. The trapped charges in the floating gate layer of NAND flash memories with an asymmetric IPD structure increased owing to an increase in the saturation voltage during programming and erasing operation.

Effect of field oxide structure on endurance characteristics of NAND flash memory

As NAND flash cell sizes have been scaled down, endurance characteristics have suffered severe limitations in the NAND flash memory. Two NAND flash cell structures, the wing spacer structure and the no wing spacer structure, have been constructed to compare their endurance characteristics. The wing spacer structure has more trap sites at the active edge area due to program/erase (P/E) cycle stress because of the short distance from the active edge to the control poly. Thus, the endurance characteristics are degraded by traps generated at the active edge area. In addition, it has been confirmed that the threshold voltage (V T) shift of the wing spacer structure was about 15.2% higher in erased cells and 10.9 % higher in programmed cells than those of the no wing spacer structure after the stress of 104 P/E cycles.

(Invited) Characteristics of Charge Trap Flash Memory with Al2O3/(Ta/Nb)Ox/Al2O3 Multi-Layer

Introduction Charge trap flash memory with high-k layers has attracted attention as a promising next-generation nonvolatile memory candidate. As a typical charge trap flash memory, the TaN/Al2O3/Si3N4/SiO2/Si structure has been widely investigated [1]. However, according to scale down of the device size, a low operation voltage is required. All high-k stack structures, such as Al2O3/HfAlOx/Al2O3 and Al2O3/La2O3/Al2O3 have been proposed to replace both Si3N4 charge trapping and SiO2tunneling layers [2, 3].It is easily understood that the conduction band offsets of charge trapping material should be lower than those of tunneling and blocking materials to make trap (program) and detrap (erase) occur in charge trapping layer during program and erase operations. The offsets of Al2O3 and Ta2O5 on Si were found to be 2.08 and 0.28 eV, respectively [4]. Hence, we should paid attention to a large difference of conduction band offset in the Al2O3/Ta2O5/Al2O3 stack structure. Furthermore, considering to reduce EOT, we employed (Ta/Nb)Oxfilms to increase k-value and keep low leakage current as charge trapping layer.In this paper, we report on the electrical performance of Pt/Al2O3/(Ta/Nb)Ox/Al2O3/Si capacitors, which were fabricated at low temperature of 200 °C, by changing thicknesses of Al2O3 blocking and tunneling layers and (Ta/Nb)Oxcharge trapping layer. Experimental The native oxide on p-Si(100) substrate was removed by diluted HF acid rinse. Al2O3 tunneling layers (4-16 nm) were deposited by PE-ALD method at 200 °C using TMA precursor and plasma oxygen gas. The (Ta/Nb)Ox charge trapping layers (1-20 nm) were subsequently deposited by ALD at 200 °C using M(NtAm)(NMe2)3 [M=Ta:Nb(1:1mol)] cocktail precursor and H2O gas. The Al2O3blocking layers (4-16 nm) were also deposited by PE-ALD at 200 °C. Finally, a 150-nm-thick Pt electrode was fabricated by sputtering. Results and Discussion A cross sectional TEM image of Pt/Al2O3/ (Ta/Nb)Ox/Al2O3/Si capacitor is shown in Fig. 1. We did not observe any severe chemical reaction in any layer, and all layers were found to be amorphous. In addition, the image reveals the presence of SiO2 interfacial layer (~1.5 nm) at Al2O3/Si interface grown during PE-ALD process. Figure 2 shows flatband voltage shift (ΔVfb) as a function of EOT in Pt/Al2O3/(Ta/Nb)Ox/Al2O3/Si capacitor. The ΔVfb and EOT values were estimated from C-V data using MIRAI-ACCEPT program [5]. Injected charge (Qinj) was kept to be 1mC/cm2. The thicknesses Al2O3 blocking layer were varied 4, 8 and 16nm, while the thickness of the Al2O3 tunneling layer was 16nm. Note that large ΔVfb value of 10 V appears because large amount of charge is trapped in the Al2O3/(Ta/Nb)Ox /Al2O3 structure. The ΔVfb value increases as thickness of the Al2O3 blocking layer increases. It suggests that the charge-trapping efficiency of (Ta/Nb)Ox layer may be lowering compared to Si3N4 layer. Therefore, although electrons captured in (Ta/Nb)Ox layer can be readily detrapped and transfer to the Al2O3 blocking layer, electrons can be trapped in the thick blocking layer. Furthermore, we also found that ΔVfb value decreases with increasing the thickness of (Ta/Nb)Oxlayer. Figure 3 shows normalized ΔVfb behavior as a function of retention time for the same capacitor shown in Fig. 2. Electric filed was applied 5MV/cm or -5MV/cm. In case of 5MV/cm, the ΔVfb degradation of the Al2O3blocking layer (16 nm) sample was not observed. On the other hand, in case of -5MV/cm, the ΔVfb values decrease with increasing retention time for all samples, regardless of thickness of the blocking layer. This indicates that the electron detrapping occurs easily across the blocking layer rather than the tunneling layer. Conclusions We have investigated memory characteristics of Pt/Al2O3/(Ta/Nb)Ox/Al2O3/Si capacitors by changing each layer thickness. We found that large charge can be trapped in Al2O3/(Ta/Nb)Ox/Al2O3 multi-layer structure even in low temperature fabrication at 200 °C.

(Invited) Charge Trapping Type SOI-FinFET Flash Memory

(Invited) Charge Trapping Type SOI-FinFET Flash Memory