Characteristics Of Double-gate MOSFETs Research Articles

Effect of Channel Engineering on Quasi-Static Capacitance-Voltage Characteristics of Double-Gate MOSFET

The quasi-static capacitance–voltage (QSCV) characteristics of 10-nm-gate-length double-gate N-type metal–oxide–semiconductor field-effect transistors (NMOSFETs) with Si, Ge, InAs, $$ {\hbox{In}}_{0.53} {\hbox{Ga}}_{0.47} {\hbox{As}} $$ , and GaAs as channel materials are studied and simulated using Silvaco ATLAS three-dimensional (3D) technology computer-aided design (TCAD) software. The QSCV approach offers the advantage of immunity against frequency dependence effects and the ability to measure small capacitances in the 100 fF range. In this device, we consider the self-consistent solution of Schrodinger’s equation with Poisson’s equation. The splitting of the conduction band into multiple subbands is considered, while there is no doping in the channel region. The effects of metal gate electrode engineering, channel engineering (Si, Ge, GaAs, $$ {\hbox{In}}_{0.53} {\hbox{Ga}}_{0.47} {\hbox{As}} $$ , and InAs), and different channel thicknesses with $$ \left( {{\hbox{Al}}_{2} {\hbox{O}}_{3} } \right) $$ as gate oxide having thickness of 0.8 nm on the QSCV characteristics are studied. A comparison of the QSCV characteristics is carried out for the above-mentioned channel materials, revealing a significant reduction in the inversion-mode QSCV characteristics for all the materials due to quantization that results in a decrease in the overall gate-to-channel capacitance and hence increases the threshold voltage of the MOS device. The QSCV characteristics are also useful to measure the oxide thickness, flat-band voltage, threshold voltage, maximum depletion region thickness, charge distribution in the dielectric, interface trap charge, and interface states between the channel and gate oxide before device fabrication.

Non-GCA modeling of near threshold I-V characteristics of DG MOSFETs

This work focuses on modeling of near threshold region (Vgs − Vt < a few kT/q) of DG (Double-Gate) MOSFETs with velocity saturation. Accurate modeling of this region is important for design of low-power analog circuits. A non-GCA (Gradual Channel Approximation) model is developed that takes the nonlinear dependence of inversion charge density on quasi-Fermi potential near threshold into account. It has been applied to both n = 1 and n = 2 velocity saturation models. The I-V characteristics generated by the model are consistent with TCAD simulations.

Performance Analysis of Nanoscale Double Gate MOSFETs with High-κ Gate Stack

The performance and characteristics of Double Gate MOSFET with high dielectric constant (high-κ) gate stack have been analyzed and compared with those of conventional pure SiO2 gate MOSFET. Quantum Ballistic Transport Model has been used to demonstrate the performance of the device in terms of threshold voltage, drain current in both low and high drain voltage regions and subthreshold swing. The effect of temperature on the threshold voltage and subthreshold characteristics has also been observed. This work reveals that improved performance of this structure can be achieved by scaling the gate length and illustrates its superiority over SiO2 gate MOSFETs in achieving long-term ITRS goals.

Effects of localized gate stack parasitic charge on current-voltage characteristics of double-gate MOSFETs with high-permittivity dielectrics and Ge-channel

In this paper we investigate the effects of localized gate stack parasitic charges on the current-voltage characteristics of double-gate (DG) MOSFET with metal/high-permittivity/Ge-channel using two-dimensional (2-D) numerical simulation. For this purpose a simulation code is developed, solving the Poisson equation on the entire device coupled self-consistently with the drift-diffusion transport equation. We show that the charges trapped at grain boundaries in the high-permittivity (high-κ) layer induce 2-D potential fluctuations in the structure, not only in the high-κ layer, but also in the underlying oxide and semiconductor regions. These potential fluctuations are shown to significantly degrade the subthreshold behavior of the drain current. The off-state drain current and the subthreshold slope increase with respect to the case where no charge is present in the gate stack. The influence of the location of the charged grain boundaries in the stack on the subthreshold parameters is also investigated using the 2-D numerical simulation code.