CNTFET Characteristics Research Articles

Simulation of Carbon Nanotube based Field Effect Transistor by Varying Gate Oxide Thickness to Explore its Electrical Property and Compare it with Standard Mosfet

Aim: The current and voltage characteristics of CNTFET and MOSFET are simulated by varying their gate oxide thickness ranging from 3.5nm to 11.5nm. Materials and Methods: The electrical conductance of CNTFET (n = 320) was compared with MOSFET (n = 320) by varying gate oxide thickness ranging from 3.5nm to 11.5nm in the NanoHUB© tool simulation environment. Results: CNTFET has significantly higher conductance (12.52 mho) than MOSFET (12.07 mho). The optimal thickness for maximum conductivity was 4nm for CNTFET and 3.5 nm for MOSFET. Conclusion: Within the limits of this study, CNTFET with the gate oxide thickness of 4 nm offers the best conductivity.

Analysis of dielectric and temperature impact on co-axial CNTFET characteristics using NEGF

Carbon nanotube (CNT) is one of the promising materials for MOS technology. In this study, the impact of dielectric materials and temperature for a certain diameter of CNT has been discussed related to ballistic CNTFET by using non-equilibrium Green’s function (NEGF) formalism. With the dielectric materials like polyethylene (2.25), hafnium silicate (11), zirconium dioxide (19) and titanium dioxide (40) the device characteristics such as drain induced barrier lowering (DIBL), Sub threshold swing (SS), carrier injection velocity (V_inj), output conductance (gm), voltage gain (AV), transconductance (gm) have been investigated.

Multivariate rational regression and its application in semiconductor device modeling

Physics equation-based semiconductor device modeling is accurate but time and money consuming. The need for studying new material and devices is increasing so that there has to be an efficient and accurate device modeling method. In this paper, two methods based on multivariate rational regression (MRR) for device modeling are proposed. They are single-pole MRR and double-pole MRR. The two MRR methods are proved to be powerful in nonlinear curve fitting and have good numerical stability. Two methods are compared with OLS and LASSO by fitting the SMIC 40 nm MOS-FET I–V characteristic curve and the normalized mean square error of Single-pole MRR is which is 4 magnitudes less than an ordinary least square. The I–V characteristics of CNT-FET and performance indicators (noise factor, gain, power) of a low noise amplifier are also modeled by using MRR methods. The results show MRR methods are very powerful methods for semiconductor device modeling and have a strong nonlinear curve fitting ability.

Statistically Modeling I–V Characteristics of CNT-FET with LASSO

With the advent of internet of things (IOT), the need for studying new material and devices for various applications is increasing. Traditionally we build compact models for transistors on the basis of physics. But physical models are expensive and need a very long time to adjust for non-ideal effects. As the vision for the application of many novel devices is not certain or the manufacture process is not mature, deriving generalized accurate physical models for such devices is very strenuous, whereas statistical modeling is becoming a potential method because of its data oriented property and fast implementation. In this paper, one classical statistical regression method, LASSO, is used to model the I–V characteristics of CNT-FET and a pseudo-PMOS inverter simulation based on the trained model is implemented in Cadence. The normalized relative mean square prediction error of the trained model versus experiment sample data and the simulation results show that the model is acceptable for digital circuit static simulation. And such modeling methodology can extend to general devices.

Study on transport characteristics of CNTFET with HALO-LDD doping structure based on NEGF quantum theory

A transport model of CNTFET is built by solving the Poisson equation and Schrödinger equation within the non-equilibrium Green's function theory. The simulation method can relate the CNTFET transport properties directly with the chiral index of CNT. For the first time, the influences of single HALO and double LDD (HLL) doping structures on the CNTFET are investigated. The results show that under the same gate-source and drain-source voltages, HLL-CNTFET reduces significantly the leakage current and the subthreshold swing and increases on-off current ratio as compared with conventional CNTFET, indicating that this new structure has better gate control ability than conventional CNTFET. HLL-CNTFET possesses a smaller drain-source conductance so that it is more suitable for analog integrated circuits application, and has a smaller threshold voltage shift so shat it can better suppress DIBL effect. The increase of channel electric field strength near the source is beneficial to the increase of the electron transport rate; and the reduction in electric field near the drain is more conductive to the suppression of hot electron effects. This study is helpful for understanding the working mechanism and exploring new features of CNTFET.

Modeling of planar carbon nanotube field effect transistor and three dimensional simulation of current-voltage characteristics

We provide a CNTFET model with planar geometry. Planar CNTFETs constitute the majority of devices fabricated to date, mostly due to their relative simplicity and moderate compatibility with existing manufacturing technologies. We explore the possibilities of using non-equilibrium Green function method to get I-V characteristics for CNTFETs. This simulator also includes a graphic user interface (GUI) of Matlab that enables parameter entry, calculation control, intuitive display of calculation results, and in-situ data analysis methods. In this paper, we review the capabilities of simulator, and give examples of typical CNTFET 3D simulations. The I-V characteristics of CNTFET are also presented.

Universal ternary logic circuit design through carbon nanotube technology

Multiple-valued logic circuits can reduce the number of operations necessary to implement a particular mathematical function and further have an advantage in terms of reduced area. Implementable CNTFET circuits have operational characteristics to approach the advantage of using MVL. Conventional nanotube diameters and using CNTFET characteristics has attracted considerable attention in the ternary logic family designs. In order to describe all ternary functions, we have achieved a new CNTFET circuit design in the universal form. In this design we have neither exclusive design problems nor mathematical equations to achieve the appropriate combination of the basic operations in the MVL fields.