Characteristics Of Carbon Nanotube Field-effect Transistors Research Articles

Enhancing high-speed digital systems: MVL circuit design with CNTFET and RRAM

Multiple Value Logic (MVL) circuits in high-speed digital systems can represent significantly more information than traditional binary logic circuits. The increasing demand for enhanced data storage capacity has driven the adoption of MVL circuits. However, designing MVL circuits presents challenges, particularly in achieving improved performance aligned with the desired threshold voltage. To address this challenge, harnessing carbon nanotube field-effect transistors (CNTFETs) has been instrumental in designing MVL circuits. CNTFETs offer distinct advantages due to their large resistors. Furthermore, substituting these resistors with Resistive Random Access Memory (RRAM) to implement Ternary logic circuits enhances storage capacity by enabling multiple resistance states within a single cell. This paper presents a novel MVL circuit design that leverages the unique characteristics of CNTFETs and RRAM. Additionally, gate implementation is explored using a Recurrent Neural Network − Long-Short Term Memory (RNN-LSTM) based Tasmanian Devil Optimization algorithm. The practical implementation uses Synopsis HSPICE software with CNTFET technology at 32 nm. A comprehensive performance analysis compares this approach with state-of-the-art solutions regarding delay, area, and power consumption. Significant reductions in area, power consumption, and transistor count are revealed with the proposed approach.

Effect of Trapped Charge Induced by Total Ionizing Dose Radiation on the Top-Gate Carbon Nanotube Field Effect Transistors

The excellent performance and radiation-hardness potential of carbon nanotube (CNT) field effect transistors (CNTFETs) have attracted wide attention. However, top-gate structure CNTFETs, which are often used to make high-performance devices, have not been studied enough. In this paper, the total ionizing dose (TID) effect of the top-gate structure CNTFETs and the influence of the substrate on top-gate during irradiation are studied. The parameter degradation caused by the irradiation- and radiation-damage mechanisms of the top-gate P-type CNTFET were obtained by performing a Co-60 γ-ray irradiation test. The results indicate that the transfer curves of the top-gate P-type CNTFETs shift negatively, the threshold voltage and the transconductance decrease when TID increases, and the subthreshold swing decreases first and then increases with the increase in TID. The back-gate transistor is constructed by using the substrate as a back-gate, and the influence of back-gate bias on the characteristics of the top-gate transistor is tested. We also test the influence of TID irradiation on the characteristics of back-gate transistors, and reveal the effect of trapped charge introduced by radiation on the characteristics of top-gate transistors. In addition, the CNTFETs that we used have obvious hysteresis characteristics. After irradiation, the radiation-induced trapped charges generated in oxide and the OH groups generated by ionization of the CNT adsorbates aggravate the hysteresis characteristics of CNTFET, and the hysteresis window increases with the increase in TID.

Energy-Efficient Ternary Multipliers Using CNT Transistors

In recent decades, power consumption has become an essential factor in attracting the attention of integrated circuit (IC) designers. Multiple-valued logic (MVL) and approximate computing are some techniques that could be applied to integrated circuits to make power-efficient systems. By utilizing MVL-based circuits instead of binary logic, the information conveyed by digital signals increases, and this reduces the required interconnections and power consumption. On the other hand, approximate computing is a class of arithmetic computing used in systems where the accuracy of the computation can be traded-off for lower energy consumption. In this paper, we propose novel designs for exact and inexact ternary multipliers based on carbon-nanotube field-effect transistors (CNFETs). The unique characteristics of CNFETs make them a desirable alternative to MOSFETs. The simulations are conducted using Synopsys HSPICE. The proposed design is compared against existing ternary multipliers. The results show that the proposed exact multiplier reduces the energy consumption by up to 6 times, while the best inexact design improves energy efficiency by up to 35 time compared to the latest state-of-the-art methods. Using the imprecise multipliers for image processing provides evidence that these proposed designs are a low-power system with an acceptable error.

Design and Optimization of Lightly Doped CNTFET Architectures Based on NEGF Method and PSO Algorithm

Optimized architectures for carbon nanotube field-effect transistors (CNTFETs) with lightly doped source and drain have been proposed. Simulations are based on self-consistent solution of two dimensional non-equilibrium Green's function (NEGF) with Poisson's equation. By utilizing special designs in the lightly doped regions of the CNTFETs, their characteristics could be improved. Four CNTFET structures have been designed and compared to the conventional CNTFET which are lightly doped source and drain (LD_CNTFET), double lightly doped source and drain (DLD_CNTFET), linear lightly doped source and drain (LLD_CNTFET) and step-linear lightly doped source and drain (SLLD_CNTFET). In order to get to the optimized electrical characteristics, for the first time, the geometry and the doping of the new designed CNTFETs have been optimized. The target of optimizations has been achieving the best Ion/Ioff, cutoff Frequency and transconductance independently. The proposed designs have been optimized based on particle swarm optimization (PSO) method. The optimized length and doping level of source and drain lightly doped regions then have been used and the features of the proposed optimized CNTFETs have been compared. The results show that with the help of the proposed designs, great improvements have been achieved in the dc and ac characteristics of CNTFETs compared to the conventional CNTFETs.

An approach to model the temperature effects on I-V characteristics of CNTFETs

A semi-empirical approach to model the temperature effects on I-V characteristics of Carbon Nanotube Field Effect Transistors (CNTFETs) is proposed. The model includes two thermal parameters describing CNTFETbehaviour in terms of saturation drain current and threshold voltage, whose values are extracted from the simulated and trans-characteristics of the device in different temperature conditions. Our results are compared with those of a numerical model online available, obtaining I-V characteristics comparable but with a lower CPU calculation time.

Systematic Approaches for Analysis and Design of Terahertz and Millimeter-Wave Integrated Circuits Using Carbon Nanotube FETs

This paper discusses design methodologies for terahertz (THz) and millimeter-wave integrated circuits using carbon nanotube field-effect transistors (CNFETs) for the first time. Two systematic approaches have been introduced throughout this paper. Pros and cons of the methods and improvements upon them are explored through both theory and simulation. The first approach is a modified $g_{m}/I_{D}$ technique, which is used for designing the CNFET analog integrated circuits. The characteristics of CNFETs are set using a novel ratio method in order to achieve optimal conditions. The second approach is a microwave method that is used for designing THz integrated circuits. This approach finds the optimal conditions by investigating activity conditions in order to achieve maximum accessible power gain of the device. This paper investigates CNFETs from a noise perspective and introduces promising results. Finally, a 1-THz high-power amplifier using microwave approach with a gain of 21.4 dB is presented for the first time.

Contact and channel resistances of ballistic and non-ballistic carbon-nanotube field-effect transistors

Recently, many research has been conducted on the carbon-nanotube field-effect transistors (CNFETs) in expectation that the CNFETs could replace metal-oxide-semiconductor field-effect transistors (MOSFETs) in the sub-10-nm era. In consideration of both ballistic conduction and nonballistic conduction, including elastic scattering, optical phonon scattering, and acoustic phonon scattering, this paper presents the simulated dependence of the coaxially-gated single-walled semiconducting CNFET characteristics on the contact and the channel lengths. When the contact length was longer than 100 nm, the CNFETs showed a constant minimal value of the contact resistance. In this case, the saturated drain current was higher than that of CNFETs with a shorter contact length. When the channel was longer than 600 nm, the channel resistance was significantly increased due to acoustic phonon scattering. When the channel was shorter than 200 - 250 nm with optical scattering, acoustic scattering or all three scattering mechanisms taken into account, the contact resistance began to become larger than channel resistance.

Effect of Gate Dielectric on Ballistic Transport of Cylindrical Carbon Nanotube MOSFET

Carbon NanoTube (CNT) channel promises near ballistic transport and is examined extensively for potential application in next-generation Nano-scale transistor. Cylindrical gate-all-around CNT field effect transistor (CNTFET) with semiconducting CNT S/D contacts and Schottky barrier CNTFET (SBCNTFET) are modeled numerically based on self-consistent solution of Poisson-Schrödinger equation with open boundary conditions within Non-Equilibrium Green’s Function formalism considering coaxial symmetry. The effect of dielectric constant (κ) and physical thickness of gate dielectric on transport characteristics of CNTFET and SBCNTFET are examined in this work. Gate capacitance, carrier injection velocity, current and therefore speed increases significantly with the inclusion of high κ dielectric and decrease in thickness. SBCNTFET also shows better performance with thin high κ dielectric layer. High trans-conductance and much lower Sub-threshold swing is visible with the inclusion of high κ gate stack.

Influence of contact height on the performance of vertically aligned carbon nanotube field-effect transistors

Vertically aligned carbon nanotube field-effect transistors (CNTFETs) have been experimentally demonstrated (J. Li et al., Carbon, 2012, 50, 4628-4632). The source and drain contact heights in vertical CNTFETs could be much higher than in flat CNTFETs if the fabrication process is not optimized. To understand the impact of contact height on transistor performance, we use a semi-classical method to calculate the characteristics of CNTFETs with different contact heights. The results show that the drain current decreases with increasing contact height and saturates at a value governed by the thickness of the oxide. The current reduction caused by the increased contact height becomes more significant when the gate oxide is thicker. The higher the drain voltage, the larger the current reduction. It becomes even worse when the band gap of the carbon nanotube is larger. The current can differ by a factor of more than five between the CNTEFTs with low and high contact heights when the oxide thickness is 50 nm. In addition, the influence of the contact height is limited by the channel length. The contact height plays a minor role when the channel length is less than 100 nm.

Comparison of simulation models for the coaxially-gated carbon-nanotube field-effect transistor

Carbon-nanotube field-effect transistors (CNFETs) have received great attention as possible successors to metal-oxide-semiconductor field-effect transistors (MOSFETs) beyond the sub-10 nm era. In this work, numerical simulations were performed on single-walled semiconducting CNFETs using a FETToy simulator and a compact model with or without a smoothing parameter. The discontinuity in the derivative of the surface potential with respect to V GS in the compact model can be remedied by employing a simple smoothing parameter. The simulated output characteristics of CNFETs with a 1.5-nm-thickgate insulator and a 3-nm-diameter nanotube channel exhibited the advantage of using a smoothing parameter. Our results show fairly good matches between the FETToy model and the compact model with a smoothing parameter of less than 5 × 10−4.

Optimization of Source/Drain Doping Level of Carbon Nanotube Field-Effect Transistors to Suppress OFF-State Leakage Current while Keeping Ideal ON-State Current

The effects of doping concentration variation in source/drain junctions on the characteristics of carbon nanotube field-effect transistors (CNFETs) have been studied in order to realize high performance CNFETs, where suppressed OFF-state leakage current and ideal maximum ON-state current were obtained. The characteristics of CNFETs with doped source/drain regions have been studied by solving the Poisson and carrier transport equations self-consistently. The transmission coefficient through the bandgap (Eg) has been calculated using the Wentzel–Kramers–Brillouin (WKB) approximation in order to take into account the band-to-band tunneling (BTBT) leakage current. The doping is characterized by the Fermi level (Ed) in a doped region which is measured from the conduction band edge. In this study, it is demonstrated that, when the power supply voltage (Vdd) is greater than the bandgap of carbon nanotubes (CNTs), optimized doping level Ed of Vdd-Eg shows the lowest OFF-state current (IOFF). On the other hand, when Vdd is smaller than Eg, IOFF monotonically decreases as Ed decreases, although the aggressively lowered doping concentration results in lower ON-state current. We also demonstrated that CNFETs with low source/drain doping concentration exhibit current saturation at higher gate voltages. The current saturation results from the fact that the injection velocity to the channel is limited by the velocity in the source region which is determined by the source doping level. We showed that, in order to avoid the current saturation, doping level should be higher than 0.3 eV, regardless of carbon nanotube diameter.

A process for high yield and high performance carbon nanotube field effect transistors

Carbon nanotube field effect transistors (CNTFETs) have been considered as one of the potential candidates for nanoelectronics beyond Si CMOS. However, it is not easy to have high performance CNTFETs with high yield currently. In this work, we proposed a local bottom-gate (LBG) CNTFETs combined with a novel device concept and optimized process technologies. High performance of CNTFET with low subthreshold swing of 139 mV/dec, high transconductance of 1.27 μS, and high I on/ I off ratio of 10 6 can be easily obtained with Ti source/drain contact after a post annealing process. Record high yield of 74% has been demonstrated. On the basis of the proposed process, lots of high performance CNTFETs can be obtained easily for advanced study on the electrical characteristics of CNTFETs in the future.

Long term investigations of carbon nanotube transistors encapsulated by atomic-layer-depositedAl2O3 for sensor applications

Single-walled carbon nanotube field-effect transistors (CNFETs) are promising functionalstructures in future micro- or nanoelectronic systems and sensor applications. Research onthe fundamental device concepts includes the investigation of the conditions for stable longterm CNFET operation. CNFET operation in ambient air leads to on-state currentdegradation and fluctuating signals due to the well-known sensitivity of the electronicproperties of the CNT to many environmental condition changes. It is the goal ofdevice and sensor research to understand various kinds of sensor–environmentinteractions and to overcome the environmental sensitivity. Here, we show that theencapsulation of CNFETs by a thermal atomic-layer-deposited (ALD) aluminium oxide (Al2O3) layer of approximately 100 nm leads to stable device operation for 260 days and reducestheir sensitivity to the environment. The characteristics of CNFETs prior to and afterAl2O3 encapsulation are comparatively investigated. It is found that encapsulationimproves the stability of the CNFET characteristics with respect to thegate threshold voltage, hysteresis width and the on-state current, while1/f noise is lowered by up to a factor of 7. Finally, CNFETs embedded in a dielectricmembrane are employed as pressure sensors to demonstrate sensor operation of CNFETsencapsulated by ALD as piezoresistive transducers.

Sub-ppm NO2 detection by Al2O3 contact passivated carbon nanotube field effect transistors

We investigate carbon nanotube field effect transistors (CNFETs) with aluminum oxide (Al2O3) passivated contacts for NO2 detection. For the CNFETs, consisting of one individual pristine single walled carbon nanotube (SWNT), the measurements indicate a strong influence of adsorbed NO2 gas molecules on the exposed CNFET channel and NO2 concentrations as low as 100 ppb were detected. Applied to the contact-SWNT interfaces, Al2O3 is a suitable material to protect the metal contacts from NO2 molecules and other undesired environmental influences. We discuss the effect of the different processing steps on the CNFET characteristics and show device recovery after short heat treatment.

Electrical characteristics of CNFETs with asymmetric gating structures

We demonstrated a straightforward technique, including device structures and associated fabrication processes to produce carbon nanotube field-effect transistors (CNFETs) which have different gate oxide thickness at two terminal junctions. Since a thinner oxide layer induces stronger gate field at one junction terminal than a thicker one, robust unipolar CNFETs were carried out. The blockage of one type of carriers is due to a Schottky barrier at the terminal junction with the thicker bottom oxide. The high ON/OFF ratios, up to 10 4, in such asymmetric gating devices show that the gate field is equally effective as the devices with uniformly thin oxide layer, and the ensuring unipolar behavior is much feasible toward nanotubes based electronics.

Nonequilibrium Green's Function Treatment of Phonon Scattering in Carbon-Nanotube Transistors

We present the detailed treatment of dissipative quantum transport in carbon nanotube field-effect transistors (CNTFETs) using the non-equilibrium Green's function formalism. The effect of phonon scattering on the device characteristics of CNTFETs is explored using extensive numerical simulation. Both intra-valley and inter-valley scattering mediated by acoustic (AP), optical (OP), and radial breathing mode (RBM) phonons are treated. Realistic phonon dispersion calculations are performed using force-constant methods, and electron-phonon coupling is determined through microscopic theory. Specific simulation results are presented for (16,0), (19,0), and (22,0) zigzag CNTFETs that are in the experimentally useful diameter range. We find that the effect of phonon scattering on device performance has a distinct bias dependence. Up to moderate gate biases the influence of high-energy OP scattering is suppressed, and the device current is reduced due to elastic back-scattering by AP and low-energy RBM phonons. At large gate biases the current degradation is mainly due to high-energy OP scattering. The influence of both AP and high-energy OP scattering is reduced for larger diameter tubes. The effect of RBM mode, however, is nearly independent of the diameter for the tubes studied here.

Response of carbon nanotube transistors to electron beam exposure

We study the effect of local charge irradiation on carbon nanotube field effect transistors (CNT-FET), in order to determine the nature of the degradation of the electrical characteristics of CNT-FETs exposed to charged beams, as for example it happens during the fabrication of the device. The study is performed by analyzing the extension of the charge distribution by means of electrical force microscopy (EFM) images, by Monte Carlo simulation of electron trajectories, and by comparing both with the change of the electrical characteristics of the devices after local irradiation with an electron beam under different conditions (beam energy and dose). The CNT-FET device characteristics show a temporary degradation, which depends on the beam energy and irradiated area, and is produced by the charging of the underlying silicon.

Air-stable n-type carbon nanotube field-effect transistors with Si3N4 passivation films fabricated by catalytic chemical vapor deposition

Air-stable n-type carbon nanotube field-effect transistors (CNTFETs) were fabricated, with Si3N4 passivation films formed by catalytic chemical vapor deposition (Cat-CVD). Electrical measurements reveal that the p-type characteristics of CNTFETs are converted to n-type after fabricating Si3N4 passivation films at 270°C. This indicates that adsorbed oxygen on the CNT sidewalls was removed during the formation process of the Si3N4 passivation films. In addition, the source-drain current of the n-type CNTFETs does not change over time under vacuum, or in air. Consequently, the n-type CNTFETs are completely protected by the Si3N4 passivation film from further effects of ambient gases. Therefore, Cat-CVD is one of the best candidates to fabricate Si3N4 passivation films on CNTFETs.

Controlling doping and carrier injection in carbon nanotube transistors

Carbon nanotube field-effect transistors (CNTFETs) fabricated out of as-grown nanotubes are unipolar p-type devices. Two methods for their conversion from p- to n-type devices are presented. The first method involves conventional doping with an electron donor, while the second consists of annealing the contacts in vacuum to remove adsorbed oxygen. A comparison of these methods shows fundamental differences in the mechanism of the transformation. The key finding is that the main effect of oxygen adsorption is not to dope the bulk of the tube, but to modify the barriers at the metal–semiconductor contacts. The oxygen concentration and the level of doping of the nanotube are therefore complementary in controlling the CNTFET characteristics. Finally, a method of controlling individually the contact barriers by local heating is demonstrated.