Chaotic Digital Communication Systems Research Articles

Frequency-Modulated Antipodal Chaos Shift Keying Chaotic Communication on Field Program Gate Array: Prototype Design and Performance Insights

Using chaos for communication can provide more robust channel security, covert transmission, and inherent support for spread-spectrum modulation. Although numerous studies have explored this technology, its practical deployment remains limited due to substantial hardware demands, complex signal processing, and a lack of efficient modulation methods for chaotic signals. In this study, a novel chaotic digital communication system is proposed and studied. A prototype of a frequency-modulated antipodal chaos shift keying (FM-ACSK) system is implemented on an Intel Cyclone V field-programmable gate array (FPGA) along with a complete mathematical model using Matlab R2022a Simulink software. Using FPGAs to implement chaotic oscillators avoids analog system problems such as component drift and high thermal instability while providing determined system parameters, rapid prototyping, and high throughput. The employment of FM over a chaotic modulation layer provides a passband operation (currently at an intermediate frequency of 10.7 MHz) while adding the benefits of carrier frequency offset robustness and constant signal envelope. Within this study, the robustness of FM-ACSK to white noise in the channel was evaluated using bit error rate, which was tested through hardware experiments and simulations. The results show the feasibility and potential performance limitations of this approach to chaotic communication system design.

Chaotic digital communication system based on field programmable gate array technology—Design and implementation

A novel universal approach for design and implementation of chaotic digital communication system based on IEEE-754 standard and field programmable gate array technology (FPGA) is proposed, combing chaos encryption with traditional cipher realization. By using the Euler algorithm and appropriate discrete processing, the continuous chaotic system is converted to a discrete chaotic system. Using FPGA hardware design system, digital chaotic sequence is generated as the key. Scrambling and expansion encryption algorithm is realized and analyzed. Driven and response of secure communication system is designed by constructing a loop including the signal and achieving chaotic synchronization between sender and receiver. Taking grid Chua chaotic system as an example, the secure communication system using FPGA hardware platform is implemented. The technical development process, algorithm flow chart, hardware design and realization result are also given.

The Cramer-Rao bound for initial conditions estimation of chaotic orbits

We derive the Cramer-Rao Lower Bound (CRLB) for the estimation of initial conditions of noise-embedded orbits produced by general one-dimensional maps. We relate this bound’s asymptotic behavior to the attractor’s Lyapunov number and show numerical examples. These results pave the way for more suitable choices for the chaotic signal generator in some chaotic digital communication systems.

ESTIMATING THE INITIAL CONDITION OF CHAOTIC ORBITS: PERFORMANCE BOUNDS

We derive the Cramér-Rao lower bound associated with the estimation of the initial condition of noise-embedded chaotic signals produced by general one-dimensional maps. We relate its asymptotic behaviour to the chaotic attractor's Lyapunov number. These results can be used to choose the chaotic generator more suitable for applications on chaotic digital communication systems.

Anti-jamming performance of chaotic digital communication systems

Among the various modulation schemes proposed for chaos-based digital communications, chaos-shift keying (CSK) and differential chaos-shift keying (DCSK) have been most thoroughly analyzed and considered for practical implementation. One important aspect of performance of any communication system is the ability to resist jamming. This area of study, however, is not available in the literature. In this paper, an analysis of antijamming performance of the coherent CSK and noncoherent DCSK systems is presented. The study includes performance analysis for the two types of systems in terms of the bit error probability under different levels of noise power, jamming power, jamming frequency and spreading factor. Computer simulations are used to verify the analytical results.