Channel Resistance Method Research Articles

Comprehensive separate extraction of parasitic resistances in MOSFETs considering the gate bias-dependence and the asymmetric overlap length

Parasitic resistances cause degradation of transconductance (gm), cutoff frequency (fT), current driving capability, and long term reliability of MOSFETs. We report a comprehensive extraction of parasitic resistance components in MOSFETs for the contact, the spreading current path, and the lightly doped drain region caused by the process, structure, and degradation. We considered the gate bias (VGS)-dependence and the asymmetric overlap length (Lov,SD) in the source and drain. We report systematically integrated extraction technique combined with the channel resistance method, the transfer length method, the dual-sweep combinational transconductance technique, the open drain method, and the parasitic junction current method. VGS-independent resistances were separated to be RSe = 6.8–6.9 Ω, RDe = 7.4–7.5 Ω, RSUB = 7.4–7.6 Ω, RSo = 1.8–2.1 Ω, and RDo = 3.2–3.5 Ω for MOSFETs with and at W/L = 50 μm/0.27 μm. VGS-dependent intrinsic resistances are obtained to be RSi = 1.9–4.4 Ω, RDi = 1.4–3.2 Ω for the same devices. The VGS-dependent intrinsic channel resistance (RCH) is extracted with different channel lengths for MOSFETs with L = 0.18 μm/0.27 μm/0.36 μm.

Hybrid Open Drain Method and Fully Current-Based Characterization of Asymmetric Resistance Components in a Single MOSFET

Separate extraction of source ( $R_{\mathrm{ S}})$ from drain resistance ( $R_{\mathrm{ D}})$ is important in the systematic modeling of electrical characteristics and investigation of physical mechanism related to the performance and reliability in MOSFETs and their integrated circuits. We report a hybrid open drain method (ODM), as a fully current-based characterization technique, for a comprehensive separation of asymmetric source and drain resistance components in a single MOSFET. In the hybrid ODM, the ODM through the parasitic bipolar transistor is combined with the dual-sweep combinational transconductance technique, the channel resistance method, and the parasitic junction current method. We fully considered the asymmetry in the source and the drain possibly caused by the layout, process, and degradation under bias. We successfully extracted the resistance components with $R_{\mathrm {{Se}}} = 6.66{{-}}7.35~\Omega $ , $R_{\mathrm {{De}}} = 7.64{{-}}8.34~\Omega $ , $R_{\mathrm {{So}}} = 0.78{{-}}8.07~\Omega $ , $R_{\mathrm {{Do}}} = 1.11{{-}}10.08~\Omega $ , and $R_{\mathrm {{SUB}}} = 6.29{{-}}9.17~\Omega $ in the n-channel MOSFETs. $R_{\mathrm {{Se}}}~(R_{\mathrm {{De}}})$ is the $V_{\mathrm {{GS}}}$ -independent external source (drain) resistance. $R_{\mathrm {{So}}}~(R_{\mathrm {{Do}}})$ is the $V_{\mathrm {{GS}}}$ -independent external spreading source (drain) resistance and $R_{\mathrm {{Si}}}~(R_{\mathrm {{Di}}})$ is the $V_{\mathrm {{GS}}}$ -dependent intrinsic source (drain) resistance, respectively. $R_{\mathrm {{SUB}}}$ is the substrate resistance. The hybrid ODM is expected to be useful in the characterization of parasitic resistances in each MOSFET with asymmetry caused by the layout, process, and degradation without using multiple devices with different channel length ( $L$ ) and width ( $W$ ) for measurement.

A Separate Extraction Method for Asymmetric Source and Drain Resistances Using Frequency-Dispersive C-V Characteristics in Exfoliated MoS2FET

Asymmetric source and drain (S/D) series resistances ( $R_{S}$ and $R_{D}$ ) are unavoidable in exfoliated MoS2 field-effect transistors (EM-FETs). Through combining the capacitance–voltage ( $C$ – $V$ ) and current–voltage characteristics, the asymmetric $R_{S}$ and $R_{D}$ values are extracted separately. First, the frequency-dispersive $C$ – $V$ characteristics are analyzed in a frequency range of 0.3–10 kHz. Second, the intrinsic $R_{S}$ and $R_{D}$ values ( $R_{S,int}$ and $R_{D,int})$ are characterized through deembedding the parasitic pad capacitances ( $C_{Pad} = C_{S,Pad}+C_{D,Pad})$ between the S/D metal and the bottom gate (G) in an overlapped region with the consideration of the structure-dependent parameters in the EM-FET. The proposed methodology is verified through comparison with the well-known channel resistance method, which is based on only the $I_{D}$ – $V_{D}$ characteristics in the linear region. Finally, $R_{S,int}$ and $R_{D,int}$ at various parasitic overlap areas are extracted separately with improved accuracy.

Reconsideration of effective channel length for metal–oxide–semiconductor field-effect transistor

The effective channel length (LEFF) of a metal–oxide–semiconductor field-effect transistor (MOSFET) as a function of gate voltage is extracted by a channel resistance method. It is observed that LEFF is strongly affected by the channel dopant nonuniformity and gate voltage. It is also weakly affected by the source–drain junction and substrate voltage. Considering these properties, we propose a new channel length definition, which is constant and obeys the classical current equation for MOSFETs with uniform channels, in order to provide a common channel length interpretation for both design and technology engineers.

Effect of Channel Dopant Distribution on Effective Channel Length Extraction

The effect of the channel dopant distribution on the effective channel length (LEFF) of metal–oxide–semiconductor field-effect transistors (MOSFETs) extracted by the channel resistance method (CRM) is studied using simple device models and experimental data. The simple device models explain how the channel dopant distribution affects extracted LEFF. The measured data for various channel structures are qualitatively explained using those models. It is found that an accurate LEFF can probably be extracted if plural samples having different dopant densities can be prepared.

Effect of channel dopant uniformity on MOSFET threshold voltage variability

The effect of the dopant uniformity in an MOSFET channel on the threshold voltage variability is studied with a simple model and the test MOSFET array which includes many MOSFETs with different channel length and width. The simple model shows that the channel uniformity in channel length direction affects the threshold voltage variability. Takeuchi coefficient as a function of the channel length is calculated from the measured threshold voltage data. The electrical channel length as a function of the gate voltage is extracted using channel resistance method. It is found that those data show the similar degree of the channel dopant uniformity for MOSFETs having various channel structures.

Amorphous In–Ga–Zn–O coplanar homojunction thin-film transistor

A fabrication process of coplanar homojunction thin-film transistors (TFTs) is proposed for amorphous In–Ga–Zn–O (a-IGZO), which employs highly doped contact regions naturally formed by deposition of upper protection layers made of hydrogenated silicon nitride (SiNX:H). The direct deposition of SiNX:H reduced the resistivity of the semiconductive a-IGZO layer down to 6.2×10−3 Ω cm and formed a nearly ideal Ohmic contact with a low parasitic source-to-drain resistance of 34 Ω cm. Simple evaluation of field-effect mobilities (μsat) overestimated their values especially for short-channel TFTs, while the channel resistance method proved that μsat was almost constant at 9.5 cm2 V−1 s−1.

Amorphous In–Ga–Zn-O thin-film transistor with coplanar homojunction structure

Amorphous In–Ga–Zn-O ( a-IGZO) thin-film transistors (TFTs) with a coplanar homojunction structure are demonstrated. The coplanar source and drain regions made of a-IGZO were formed by depositing a hydrogenated silicon nitride (SiN X:H) layer onto the a-IGZO layer. The a-IGZO regions on which the SiN X:H layer was directly deposited showed the low resistivity of 4.7 × 10 −3 Ω cm and degenerated conduction. The fabricated TFT showed excellent transfer and output characteristics with a field-effect mobility of 11 cm 2 V − 1 s − 1 , a subthreshold swing of 0.17 V decade − 1 , and an on-to-off current ratio larger than 1 × 10 9. The width-normalized source-to-drain resistance ( R sd W) calculated using a channel resistance method was 51 Ω cm. This TFT also showed good stability over environment change and under electrical stress.

Accurate Extraction of Effective Channel Length and Source/Drain Series Resistance in Ultrashort-Channel MOSFETs by Iteration Method

This paper presents a new extraction method for effective channel length (L eff) and source/drain series resistance (R SD) in ultrashort-channel MOSFETs using an iterative process, which is a modified channel resistance method (CRM). Although conventional methods for extracting L eff and R SD, such as the channel resistance and shift-and-ratio methods, are considered to be the most consistent techniques, they are not valid for shorter channel transistors, such as the total resistance (R tot = V DS/I DS) of MOSFETs, and do not scale proportionately with poly-gate length (L poly). This error results from the fact that these methods assume the effective mobility f(mueff) of long- and short-channel transistors to be the same. This assumption inevitably lowers the accuracy of the extracted channel length in ultrashort-channel MOSFETs. Therefore, an improved CRM using an iterative procedure has been proposed. This iteration method takes into account the fact that mobility is degraded in shorter channel devices. By compensating for the mobility in long-channel devices, more accurate approximations for L eff and R SD are extracted compared to conventional methods.

Grain size effects on contact resistance of top-contact pentacene TFTs

Multiple top-contact OTFTs with various channel lengths ( L c) were successfully scaled-down to the L c of 1.8 μm by using the membrane shadow mask and the interface between the evaporated Au and pentacene was analyzed based on the channel resistance method. For large grain pentacene (S-80) deposited at 80 °C, the parasitic resistance ( R p) at V GS = −20 V has 1.8 ± 0.2 kΩ cm, whereas for small grain pentacene (S-20) deposited at 20 °C has 4.2 ± 0.2 kΩ cm, which means that R p depends on the grain size of pentacene. The grain size and grain boundary trap density for pentacene can be possibly origins to determine R p, which is critically correlated with bulk transport in pentacene. The grain boundary trap density ( N t) for S-80 and S-20 was extracted as (5.6 ± 0.5) × 10 11 and (1.2 ± 0.3) × 10 12 cm −2 from the Levinson plots, respectively. In addition, activation energy of R p for S-80 is in the range from 42 to 48 meV, whereas for S-20 is from 72 to 108 meV.

Definition of effective channel length (L eff) in deep submicron MOSFETs based on numerically simulated surface potential

A new definition of L eff which agrees well with electrical measurements using the channel resistance method is proposed, based on numerically simulated surface potential. Using the L eff definition, the physics underlying the fact that L eff can be considerably longer than the metallurgical channel length L eff is explored, and the independence of L eff on substrate bias V sub is clarified. The gate bias dependence of L eff in LDD MOSFET is clearly reflected by the proposed L eff definition.

A capacitance method to determine channel lengths for conventional and LDD MOSFET's

A simple method for determining the channel length and in situ gate-oxide thickness of MOSFETs is described. The method is based on the linear relationship between the intrinsic gate capacitance and effective channel length. Measurements from two gate biases on devices of different channel lengths are sufficient to obtain a full characterization. In contrast to the channel-resistance method, the accuracy of the capacitance method is independent of the source-drain and contact series resistance. It can, therefore, be used for conventional as well as lightly-doped drain (LDD) devices. Channel length and gate-oxide thickness determined by this method are given for conventional and LDD MOSFET's. For conventional MOSFET's, the new method agrees with the traditional effective length measurements to better than 0.1 µm.