Channel Hot Electron Stress Research Articles

Electrical Characteristics of the Uniaxial-Strained nMOSFET with a Fluorinated HfO₂/SiON Gate Stack.

The channel fluorine implantation (CFI) process was integrated with the Si3N4 contact etch stop layer (SiN CESL) uniaxial-strained n-channel metal-oxide-semiconductor field-effect transistor (nMOSFET) with the hafnium oxide/silicon oxynitride (HfO2/SiON) gate stack. The SiN CESL process clearly improves basic electrical performance, due to induced uniaxial tensile strain within the channel. However, further integrating of the CFI process with the SiN CESL-strained nMOSFET exhibits nearly identical transconductance, subthreshold swing, drain current, gate leakage and breakdown voltage, which indicates that the strain effect is not affected by the fluorine incorporation. Moreover, hydrogen will diffuse toward the interface during the SiN deposition, then passivate dangling bonds to form weak Si-H bonds, which is detrimental for channel hot electron stress (CHES). Before hydrogen diffusion, fluorine can be used to terminate oxygen vacancies and dangling bonds, which can create stronger Hf-F and Si-F bonds to resist consequent stress. Accordingly, the reliability of constant voltage stress (CVS) and CHES for the SiN CESL uniaxial-strained nMOSFET can be further improved by the fluorinated HfO2/SiON using the CFI process. Nevertheless, the nMOSFET with either the SiN CESL or CFI process exhibits less charge detrapping, which means that a greater part of stress-induced charges would remain in the gate stack after nitrogen (SiN CESL) or fluorine (CFI) incorporation.

Stress immunity enhancement of the SiN uniaxial strained n-channel metal–oxide–semiconductor field-effect-transistor by channel fluorine implantation

Channel fluorine implantation (CFI) has been successfully integrated with silicon nitride contact etch stop layer (SiN CESL) to investigate electrical characteristics and stress reliabilities of the n-channel metal–oxide–semiconductor field-effect-transistor (nMOSFET) with HfO2/SiON gate dielectric. Although fluorine incorporation had been used widely to improve device characteristics, however, nearly identical transconductance, subthreshold swing and drain current of the SiN CESL strained nMOSFET combining the CFI process clearly indicates that stress-induced electron mobility enhancement does not affect by the fluorine incorporation. On the other hand, the SiN CESL strained nMOSFET with fluorine incorporation obviously exhibits superior stress reliabilities due to stronger Si–F/Hf–F bonds formation. The channel hot electron stress and constant voltage stress induced threshold voltage shift can be significantly suppressed larger than 26% and 15%, respectively. The results clearly demonstrate that combining the SiN CESL strained nMOSFET with fluorinated gate dielectric using CFI process becomes a suitable technology to further enhance stress immunity.

Characteristics of the SiN Uniaxial Strained NMOSFET with Channel Fluorine Implantation

Channel fluorine implantation (CFI) has been successfully integrated with silicon nitride contact etch stop layer (SiN CESL) to further improve the channel hot electron stress (CHES) and constant voltage stress (CVS) reliability of n-channel metal-oxide-semiconductor field-effect-transistor with HfO2/SiON gate stack. Although the improvement of transconductance, drain current and subthreshold swing due to the fluorine passivation is screened out by the effect of uniaxial tensile strain, the result clearly demonstrates that integrating the CFI process in the SiN CESL-strained device can further suppress the CHES- and CVS-induced threshold voltage shift.

Impact of strain on hot electron reliability of dual-band power amplifier and integrated LNA-mixer RF performances

Abstract Channel hot-electron-induced degradation on strained MOSFETs is examined experimentally. BSIM stressed model parameters are extracted from measurement and used in Cadence SpectreRF simulation to study the impact of channel hot electron stress on dual-band class-E power amplifier and integrated low-noise amplifier-mixer RF performances. Channel hot electron effect decreases power efficiency of dual-band class-E power amplifier and increases the noise figure of low-noise amplifier-mixer combined circuit.

Study on the degradation of NMOSFETs with ultra-thin gate oxide under channel hot electron stress at high temperature

This paper studies the degradation of device parameters and that of stress induced leakage current (SILC) of thin tunnel gate oxide under channel hot electron (CHE) stress at high temperature by using n-channel metal oxide semiconductor field effect transistors (NMOSFETs) with 1.4-nm gate oxides. The degradation of device parameters under CHE stress exhibits saturating time dependence at high temperature. The emphasis of this paper is on SILC of an ultra-thin-gate-oxide under CHE stress at high temperature. Based on the experimental results, it is found that there is a linear correlation between SILC degradation and Vh degradation in NMOSFETs during CHE stress. A model of the combined effect of oxide trapped negative charges and interface traps is developed to explain the origin of SILC during CHE stress.

Anomalous Gate-Edge Leakage Induced by High Tensile Stress in NMOSFET

Anomalously high gate tunneling current, induced by high-tensile-stress memorization technique, is reported in this letter. Carrier-separation measurement method shows that the increased gate tunneling current is originated from the higher gate-to-source/drain (S/D) tunneling current, which worsens when channel length is getting shorter. Also, the device with enhanced tensile strain exhibits 9% higher gate-to-S/D overlapping capacitance. These data indicate that the anomalously high gate tunneling current could be attributed to the high tensile strain that induces the effects of excessive lightly doped dopant diffusion and higher gate-edge damage. The proposed inference is confirmed by channel hot-electron stress.

Impact of the strained SiGe source/drain on hot carrier reliability for 45nm p-type metal-oxide-semiconductor field-effect transistors

In this letter, the impact of the uniaxial strain SiGe source/drain (S/D) on hot carrier reliability in 45nm p-type metal-oxide-semiconductor field-effect transistor is investigated in detail. We find that the extra mechanical stress deteriorates the gate oxide and/or generates interface states significantly, resulting in the hot carrier degradation dominantly driven by the drain avalanche hot carrier stress (Vg=1∕2Vd), as opposed to the channel hot electron stress (Vg=Vd), the well-known dominant mechanism for hot carrier degradation in the conventional deep submicron devices. A model to explain the mechanism of these observations is proposed.

Electrical and Temperature Stress Effects on Class-AB Power Amplifier Performances

Normalized degradations of drain efficiency and output power as a function of conduction angle, maximum drain current, and maximum output voltage are modeled. Good agreement between the model predictions and Cadence radio-frequency simulation results is obtained. The output power and efficiency of class-AB power amplifiers (PAs) degrade with channel hot electron stress due to reduced conduction angle, drain current, and output voltage. The degradation is enhanced at high temperature. In addition, the PA third-order input intercept point and adjacent channel power ratio all decrease with stress

Stress-induced width-dependent degradation of low-temperature polycrystalline silicon thin-film transistor

This study characterizes the stress-induced subthreshold degradation effect in low-temperature polycrystalline silicon thin-film transistors (LTPS-TFTs) formed using sequential lateral solidified (SLS) crystallization on a glass substrate. The SLS process is adopted to improve carrier mobility by increasing the grain size. The deterioration of the innate subgrain boundaries that are induced by channel hot-electron stress causes these transistors to exhibit double-hump subthreshold characteristics which become more prominent as the width of the channel increases. A physical theory and a proposed transistor network model accurately explain and predict the width-dependent subthreshold degradation characteristics of these stress LTPS-TFTs.

Performance, Degradation Monitors, and Reliability of the CHISEL Injection Regime

This work reviews recent results concerning the performance and reliability of the channel initiated secondary electron (CHISEL) injection regime, often used to boost the programming speed of Flash memories. In order to relate the CHISEL behavior to the physical conditions existing in the device, the injection efficiency of CHISEL is studied on single transistors. A comparison between the degradation in the CHISEL injection and in the channel hot electron (CHE) stress regime has been also performed, and the most relevant electrical monitor for the degradation is assessed. It is confirmed that the CHISEL mechanism is promising for the realization of faster and more efficient Flash memory cells.

On interface and oxide degradation in VLSI MOSFETs. I. Deuterium effect in CHE stress regime

This paper analyzes in detail the generation of interface states (N/sub it/) and stress-induced leakage current (SILC) during channel hot electron (CHE) stress experiments in the context of a possible hydrogen/deuterium (H/D) isotope effect. Our results show that N/sub it/ generation is related to the hydrogen release (HR) at the Si-SiO/sub 2/ interface at relatively high V/sub G/ where a large isotope effect is found. Instead, for gate voltages (V/sub G/) favorable for hot hole injection (HHI) the N/sub it/ creation becomes a unique function of hole fluence and the isotope effect disappears. In the studied stress conditions, we found no experimental evidence supporting a causal relation between SILC generation and HR because no isotope effect is observed even when the corresponding N/sub it/ measurements reveal a very different D/H release rate. Similar to N/sub it/ generation, we found that SILC becomes a unique function of hole fluence at low stress V/sub G/. Relevant implications and extensions of these results to the Fowler-Nordheim (FN) tunneling stress conditions are discussed in Pt. II.

Deuterium passivation of interface traps in MOS devices

The mechanism for deuterium passivation of interface traps in MOS devices is studied. Normal channel hot electron (CHE) stress was performed on hydrogen-passivated devices to locally desorb hydrogen from the interface at the drain region. The stressed devices were annealed in deuterium at 400/spl deg/C, resulting in a full recovery of device characteristics. These devices were then subjected to CHE stress again in two modes. Some of them were stressed in the normal mode while others were stressed in the reverse mode in which the source and drain were interchanged. Compared with hydrogenated devices, these deuterated devices under the normal stress exhibit a significant reduction in interface trap generation and threshold voltage shift. In contrast, insignificant reliability improvement was observed for the reverse stress case. The asymmetric degradation behaviors on these deuterated devices suggest that the effectiveness of implementing deuterium to improve device reliability is limited by its replacement of pre-existing hydrogen at the oxide/silicon interface.

A novel experimental technique for the lateral profiling of oxide and interface state charges in hot-hole degraded n-MOSFETs

A new experimental technique, based on gate-to-drain capacitance C/sub gd//sup s/ and charge pumping (CP) current, is proposed for the lateral profiting of oxide and interface state charges in the LDD region of the n-MOSFETs. The device is injected with hot holes, which are subsequently removed by a low-level channel hot-electron stress. The degree of neutralization is monitored by C/sub gd//sup s/ until complete annihilation of trapped holes is realized. This allows the effects of oxide and interface state charges on CP characteristics to be clearly distinguished, and the spatial profiles of the two charges to be separately determined.

Profiling interface traps in MOS transistors by the DC current-voltage method

Position profiling the interface trap density along the channel length of metal-oxide-silicon transistors by the Direct-Current Current-Voltage method is illustrated for five density variations: zero, peaked in drain junction space-charge layer, constant in channel, nonconstant in channel, and peaked in drain junction space-charge layer and nonconstant in channel. The interface trap densities were monitored by MOS transistor's d.c. body current and the density profiles were obtained from the body-drain and body-source differential conductance versus drain or source bias voltage. An experimental demonstration is given for a 1.6 μm n-channel Si MOS transistor with about 10/sup 11/ traps/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> generated by channel hot electron stress.

Comparison of neutral electron trap generation by hot-carrier stress in n-MOSFET's with oxide and oxynitride gate dielectrics

A comparative study of neutral electron-trap generation due to hot-carrier stress in n-MOSFETs with pure oxide, NH/sub 3/-nitrided oxide (RTN), and reoxidized nitrided oxide (RTN/RTO) as gate dielectrics is reported. Results show that neutral electron trap generation is considerably suppressed by nitridation and reoxidation. The nature of neutral traps is described based on the kinetics of trap filling by electron injection into the gate dielectrics immediately after channel hot-electron stress (CHES). Improved endurance of the RTN and RTN/RTO oxides is explained using physical models related to interfacial strain relaxation.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Gate-induced drain leakage current degradation and its time dependence during channel hot-electron stress in n -MOSFETs

The effects of channel hot-electron stress on the gate-induced drain leakage current (GIDL) in n-MOSFETs with thin gate oxides have been studied. It is found that under worst case stress, i.e. a high density of generated interface states Delta D/sub it/, the enhanced GIDL exhibits a significant drain voltage dependence. Whereas Delta D/sub it/ increases significantly the leakage current at low V/sub d/, it has minor effects at high V/sub d/. On the other hand, the electron trapping was found to increase the leakage current rather uniformly over both low and high V/sub d/ regions. In addition, GIDL degradation can be expressed as a power law time dependence (i.e. Delta I/sub leak/=A.t/sup n/), and the time dependence value n varies according to the dominant damage mechanism (i.e. electron trapping against Delta D/sub it/), similar to that reported for on-state device degradation.

Improved reliability characteristics of submicrometer nMOSFETs with oxynitride gate dielectric prepared by rapid thermal oxidation in N/sub 2/O

Submicrometer MOSFETs with ultrathin oxynitride gate dielectric grown in pure N/sub 2/O ambient were studied. The peak mobility of oxynitride is 5% lower than that of control oxide. However, the oxynitride shows 10% less mobility degradation under high normal field. Compared with the control oxide device, the oxynitride device shows significantly less degradation under channel hot-electron stress. The lifetime of the oxynitride device is approximately one order of magnitude longer than that of the control oxide sample. Significant improvement of device reliability is due to the nitrogen incorporation during the oxidation process. >

Hot-electron degradation of n-channel polysilicon MOSFETs

The stability of the hydrogen passivation in hydrogenated n-channel polysilicon MOSFETs has been studied under thermal stress and hot-electron stress at elevated temperatures. Although the hydrogen passivation is stable at 150 degrees C, channel hot-electron stress at high temperatures appears to create additional grain boundary traps, presumably by breaking the Si-H bonds at the grain boundaries. This mechanism is in addition to the creation of acceptor-type fast interface states that occur in bulk MOSFETs. >

The effect of channel hot electron stress on a.c. device characteristics of MOSFETs

The effect of channel hot electron, CHE, stress on small signal parameters such as gain and 1/ f noise of NMOS transistors operating in the linear region was studied. It is shown that the dominant degradation mechanism is charge trapping in the gate oxide. A qualitative model that allows extraction of the length of the damaged region as well as the effective threshold voltage of the active device is suggested. A critical analysis of the charge pumping technique when applied to devices with nonuniform spacial distribution of trapped charges is presented.

A measurement method for the increase of digital switching time due to hot-electron stress

Channel hot-electron (CHE) injection poses a reliability problem for n-channel field-effect transistors with small design rules. One often assesses the reliability of a particular fabrication process and design by subjecting individual transistors, instead of an entire circuit, to continuous or pulsed voltage stress. Simple inspection of the linear region transconductance degradation and threshold voltage shift of the individual devices, however, does not yield direct information on the circuit performance impact of channel hot-electron stress. In this letter we describe a simple measurement method for the extraction of the increase of digital switching time due to channel hot-electron stress. One performs this measurement on discrete transistors so that reliability tests still employ these individual devices. We obtain good agreement between this method and a direct measurement of the increased switching time of a CMOS inverter. We also find that the switching time changes negligibly even when the linear transistor characteristics are severely degraded if this swiching delay is measured with the same source and drain terminals as were employed for the hot-electron stress.