Channel Hot Carrier Degradation Research Articles

A Comparison of Electroluminescence Spectra From Plan View and Cross-Sectioned AlGaN/GaN Devices

We report on a comparison of electroluminescence (EL) spectra measured in plan view versus on a cross-sectioned face of the same AlGaN/GaN device for the first time. Because EL emission can be more intense under optically opaque metal structures, a difference was expected. We observed and quantified the difference in EL intensity and the extracted electron temperature. We discuss the effect on the rate of proposed channel hot-carrier degradation. Device simulations were used to gain insight on the expected spatial distribution of hot electrons within the channel. Last, spectra acquired on the cross-sectioned face were found to be free of interference artifacts common in plan view that could complicate the interpretation of the spectral data.

A Defect-Centric Analysis of the Temperature Dependence of the Channel Hot Carrier Degradation in nMOSFETs

The defect-centric distribution is used to study the temperature dependence of channel hot carrier (CHC) degradation in deeply scaled nMOSFETs. We analyze the temperature dependence in terms of the defect-centric parameters. The total number of traps is observed to increase with temperature, whereas the average threshold voltage shift produced by a single charged defect, i.e., <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\eta$</tex-math></inline-formula> , is confirmed to be independent of the temperature, as previously shown for bias temperature instability. By using the defect-centric analysis, we estimate the activation energy of the threshold voltage shift and that of the number of charged traps per device, which are directly linked to the CHC degradation.

Defect-Centric Distribution of Channel Hot Carrier Degradation in Nano-MOSFETs

The defect-centric distribution is used, for the first time, to study the channel hot carrier (CHC) degradation. This distribution has been recently proposed for bias temperature instability (BTI) shift and we show that it also successfully describes the CHC behavior. This distribution has the advantage of being described by two physics-based parameters, the average threshold voltage shift produced by a single charge η and the number of stress-induced charged traps N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</sub> . We study the behavior of η and N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</sub> on nFETs with different geometries for different CHC stress times. As in the case of BTI, we observe that: 1) during the CHC stress, η is constant and N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</sub> increases at the same rate of ΔV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> and 2) η scales as 1/Area. We show that the density of charged traps induced by CHC stress strongly increases with reducing channel length, in contrast to BTI, where the density of charged traps is independent of the device geometry. The defect analysis enabled by the defect-centric statistics can be used to deepen our understanding of CHC degradation in nanoscale MOSFETs, where the defects are reduced to a numerable level.

A Conductive AFM Nanoscale Analysis of NBTI and Channel Hot-Carrier Degradation in MOSFETs

This paper addresses the impact of different electrical stresses on nanoscale electrical properties of the MOSFET gate dielectric. Using a conductive atomic force microscope (CAFM) for the first time, the gate oxide has been analyzed after bias temperature instability (BTI) and channel hot-carrier (CHC) stresses. The CAFM explicitly shows that while the degradation induced along the channel by a negative BTI stress is homogeneous, after a CHC stress different degradation levels can be distinguished, being higher close to source and drain.

PMOSFET의 채널 길이에 따른 NBTI 스트레스와 CHC 스트레스의 신뢰성 특성 비교 분석

Channel length dependence of NBTI (negative bias temperature instablilty) and CHC (channel hot carrier) characteristics in PMOSFET is studied. It has been considered that HC lifetime of PMOSFET is larger than NBTI lifetime. However, it is shown that CHC degradation is greater than NBTI degradation for PMOSFET with short channel length. 1/f noise and charge pumping measurement are used for analysis of these degradations.

Impact of the Substrate Orientation on CHC Reliability in n-FinFETs—Separation of the Various Contributions

In this paper, we perform a comparative analysis of the degradation induced by a channel hot carrier (CHC) in bulk n-FinFETs with rotated (100) and nonrotated (110) sidewall surfaces. CHC degradation includes several components, and separating each contribution is necessary for identifying different mechanisms in devices with different surface orientations. First, the permanent and recoverable components are separated based on the recovery phenomenon after the CHC stress, ascribed to the electron detrapping from the oxide bulk defects. Then, the contribution of generated interface states to the permanent component is quantified by charge pumping measurements. The nonrotated bulk FinFETs showed higher threshold voltage degradation at the maximum bulk current stress condition due to the higher interface precursor defect density compared with the rotated devices. On the other hand, the rotated bulk FinFETs showed higher threshold voltage degradation at the stress condition of V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> = V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> due to higher bulk defect trapping, ascribed to the lower physical oxide thickness.

Improved Channel Hot-Carrier Reliability in $p$-FinFETs With Replacement Metal Gate by a Nitrogen Postdeposition Anneal Process

Channel hot-carrier (CHC) reliability in <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$p$</tex></formula> -FinFET devices is studied related to the postdeposition anneal (PDA) process. Clearly reduced CHC degradation is observed with <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\hbox{N}_{2}$</tex></formula> -PDA at the <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX"> $V_{G} = V_{D}$</tex></formula> stress condition. The interface defect density degradation calculated from the subthreshold slope is similar in the reference and PDA devices. However, the pre-existing high- <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$k$</tex></formula> bulk defect is lower in the PDA-treated device as observed by the low-frequency-noise measurement. This leads to less hot/cold-carrier injection into the bulk defects at the high field under the <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX"> $V_{G} = V_{D}$</tex></formula> condition, where a higher charge trapping component is expected than under the classical <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$V_{G} \sim V_{D}/\hbox{2}$</tex></formula> condition. The responsible bulk defect is pre-existing, not generated during the CHC stress as proven by the stress-induced leakage current analysis.

Channel Hot Carrier Degradation Mechanism in Long/Short Channel $n$-FinFETs

The channel hot carrier degradation mechanisms in n-FinFET devices are studied. In long channel devices, interface degradation by hot carriers mainly degrades the device at the maximum impact ionization condition (VG ~ VD/2). At higher VG closer to VD, cold and hot carrier injection to the oxide bulk defect increases and dominates at the VG=VD stress condition. On the other hand, in short channel devices, hot carriers are generated continuously with respect to VG and highly at VG=VD, and this hot carrier injection into the oxide bulk defect is the main degradation mechanism.

A comprehensive study of channel hot-carrier degradation in short channel MOSFETs with high-k dielectrics

This paper presents a comprehensive study on channel hot-carrier (CHC) degradation in short channel MOSFETs with high-k dielectric. Different reliability scenarios are analyzed, i.e., temperature influence, impact of high ID and dynamic operation conditions. To explain the CHC damage behavior in short channel devices, we divide the total CHC degradation in two components: the classical CHC damage located at drain side and the degradation produced by the voltage drop over the gate dielectric, which can be considered as bias temperature instability (BTI).

Voltage Ramp Stress for Hot-Carrier Screening of Scaled CMOS Devices

The voltage ramp stress (VRS) methodology is introduced for hot-carrier screening of advanced CMOS devices. It is demonstrated that the voltage and the time dependence measured with VRS are in good agreement with the constant voltage stress procedure, yielding equivalent reliability modeling parameters for conventional poly-Si/SiON and metal-gate/high-k n-channel MOSFETs. Since little knowledge about the transistor design is required for VRS testing, it becomes the preferred procedure for process screening and monitoring of advanced CMOS devices. Additionally, the VRS method is used to quantify channel hot-carrier degradation by correcting for bias temperature instability contributions during hot-carrier injection-VRS test.

Plasma Nitrided Oxide와 Thermally Nitrided Oxide를 적용한 NMOSFET의 Flicker Noise와 신뢰성에 대한 비교 분석

In this paper, flicker noise characteristic and channel hot carrier degradation of NMOSFETs with plasma nitrided oixde (PNO) and thermally nitrided oxide (TNO) are analyzed in depth. Compared with NMOSFET with TNO, flicker noise characteristic of NMOSFET with PNO is improved significantly because nitrogen density in PNO near the Si/ interface is less than that in TNO. However, device degradation of NMOSFET with PNO by channel hot carrier stress is greater than that with TNO although PMOSFET with PNO showed greater immunity to NBTI degradation than that with TNO in previous study. Therefore, concurrent investigation of the reliability as well as low frequency noise characteristics of NMOSFET and PMOSFET is required for the development of high performance analog MOSFET technology.

CHC degradation of strained devices based on SiON and high- k gate dielectric materials

A comparison between the Channel Hot-Carrier (CHC) degradation on strained pMOSFETs with SiGe source/drain (S/D) based on different gate dielectric materials, as SiON or HfSiON, has been done. The influence of the device channel orientation, channel length and temperature on the CHC damage has been studied.

Gate Voltage Influence on the Channel Hot-Carrier Degradation of High-$k$ -Based Devices

In ultrascaled complimentary metal-oxide-semiconductor technologies, the lucky-electron model does not describe correctly Channel Hot-Carrier (CHC) degradation for typical transistor test conditions independently of the gate dielectric (SiO2 or high- k). A new model to describe the CHC degradation behavior in n-channel metal-oxide field-effect transistors, based on the dominant role of the gate voltage into the total CHC stress, is presented. This new model can be applicable to long- and short-channel transistors with high- k or SiO2 as a dielectric.

Processing dependences of channel hot-carrier degradation on strained-Si p-channel metal-oxide semiconductor field-effect transistors

The channel hot-carrier (CHC) degradation in metal-oxide semiconductor field-effect transistors based on a high-k dielectric with strained-Si/relaxed Si1−xGex structures has been little studied so far. However, due to the high mobility enhancement observed in these samples, a deeper study of the CHC impact on them is necessary. In this article, the effects of the Ge content, overgrowth, channel length, and operating temperature on the CHC degradation have been analyzed. The results show that devices with higher mobility suffer larger CHC aging both at room temperature and in the elevated temperature range.

Tradeoff Between Hot Carrier and Negative Bias Temperature Degradations in High-Performance $\hbox{Si}_{1 - x}\hbox{Ge}_{x}$ pMOSFETs With High-$k$/Metal Gate Stacks

Analyzed herein is the effect of different germanium (Ge) concentrations on negative bias temperature instability (NBTI) and channel hot carrier (CHC) degradations in high-performance Si1-xGex pMOSFETs. It is shown that higher concentrations result in less NBTI degradation due to the increased barrier height between the SiGe and high-k dielectric interface, but it causes greater CHC degradation due to the decreased channel bandgap with higher Ge concentrations. Therefore, the tradeoff between NBTI and HC degradations for different Ge concentrations should be considered when developing high-performance Si1-xGex pMOSFETs.

Simulation of the hot‐carrier degradation in short channel transistors with high‐K dielectric

AbstractThe degradation produced by channel hot‐carrier (CHC) on short channel transistors with high‐k dielectric has been analyzed. For short channel transistors (L&lt;0.15 µm), the most damaging stress condition has been found to be VG=VD instead of the ‘classical’ VG=VD/2 determined for long channel transistors. In this work, experimentally validated simulations have been performed to demonstrate that this shift is not caused by the presence of the high‐k layer but due to short channel effects. Furthermore, the CHC degradation lifetime has been evaluated, revealing larger operating voltages for high‐k than for SiO2‐based transistors. Copyright © 2010 John Wiley &amp; Sons, Ltd.

Channel Hot-Carrier Degradation in Short-Channel Transistors With High- $k$/Metal Gate Stacks

Channel hot-carrier (CHC) degradation in nMOS transistors is studied for different SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /HfSiON dielectric stacks and compared to SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> . We show that, independent of the gate dielectric, in short-channel transistors, the substrate current peak (used as a measure for the highest degradation) is at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> = V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> , whereas for longer channels, the maximum peak is near V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> = V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> /2. We demonstrate that this shift in the most damaging CHC condition is not caused by the presence of the high- k layer but by short-channel effects. Furthermore, the CHC lifetime of short-channel transistors was evaluated at the most damaging condition V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> = V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> , revealing sufficient reliability and even larger operating voltages for the high-k stacks than for the SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> reference.

Competing Degradation Mechanisms in Short-Channel Transistors Under Channel Hot-Carrier Stress at Elevated Temperatures

The temperature dependence of channel hot-carrier (CHC) degradation in n-MOS transistors with high- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> dielectrics has been studied. The analysis starts from the most damaging CHC stress conditions at room temperature ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> = <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> /2 for long channels and <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> = <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> for short channels). We find that, for long-channel transistors, the CHC degradation decreases at high temperature, while for short-channel transistors, an increase is observed. In this paper, a new picture to explain the observed increment of CHC damage with temperature for short-channel transistors with high- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> dielectric is presented. We demonstrate that the total CHC degradation consists of two components: the classical CHC damage located at the drain side and the degradation produced by the voltage drop over the gate dielectric, which can be considered a positive bias temperature instability (PBTI) effect. Particularly for short transistors stressed at high temperatures, this PBTI component dominates the total CHC degradation.

Channel hot-carrier degradation in pMOS and nMOS short channel transistors with high-k dielectric stack

A comparison between pMOS and nMOS short channel transistors with high-k dielectric subjected to channel hot-carrier (CHC) stress is presented. Smaller CHC degradation is observed in pMOS devices. At high temperature, the CHC degradation increases for pMOS and nMOS. The temperature dependence of the CHC degradation has been explained, for both transistor types, by considering a larger influence of a bias temperature instability (BTI)-related component of the total CHC induced degradation.

Channel hot-carrier degradation under AC stress in short channel nMOS devices with high-k gate stacks

The channel hot-carrier (CHC) degradation in nMOS transistors with high-k dielectric subjected to different AC stress configurations was studied. The influence of the gate AC stress waveform parameters on the CHC degradation was analysed, when a constant drain voltage was applied. For short channel devices, CHC degradation has been found to be dependent on duty-cycle and rise/fall times and independent of frequency. These results have been observed independently of the gate dielectric material (SiO 2 or high-k). Moreover, the CHC damage in a nMOS transistor subjected to stress conditions which simulate its operation within a CMOS inverter has been also analysed. Lower degradation is observed in this case.