Channel Effects In MOSFETs Research Articles

Analysis of different parameters of channel material and temperature on threshold voltage of CNTFET

Carbon nanotubes have some unique features and special properties that offer a great potential for nano-electronic devices. In this paper, we have analyzed the effect of chiral vector, metal work function, channel length and High-K dielectric on threshold voltage of CNTFET devices. We have also compared the effect of oxide thickness on gate capacitance and justified the advantage of CNTFET over MOSFET in nanometer regime. Simulation on HSPICE tool shows that high threshold voltage can be achieved at low chiral vector in CNTFET. It is also observed that the temperature has a negligible effect on threshold voltage of CNTFET. After that we have simulated and observed the effect of channel length variation on threshold voltage of CNTFET as well as of MOSFET devices and given a theoretical analysis on it. We found an unusual, yet, favorable characteristics that the threshold voltage increases with decreasing channel length in CNTFET devices in deep nanometer regime especially when the gate length is around 10nm; which is quite contrary to the well known short channel effects in MOSFET. It is observed that at or below 10nm channel length the threshold voltage increases rapidly in case of CNTFET device whereas in case of MOSFET device the threshold voltage decreases drastically.

Tools for contactless testing and simulation of CMOS circuits

Short channel effects in MOSFETs are responsible for time-dependent hot-carrier luminescence, synchronous with the switching transitions in CMOS circuits. We propose an optical non-invasive inspection technique for high-speed signals, based on a high sensitivity solid-state photodetector with sharp time resolution. This tool is able to probe the fast electrical waveforms propagating through ULSI circuits without electrically loading the circuit under test. The measured time resolution of 50 ps allows an equivalent analog bandwidth of about 20 GHz. From the experimental results and the luminescence characterization of single transistors, we propose a SPICE model able to foresee the photoemission in complex ULSI circuits, down to transistor level. The optical testing equipment and the SPICE modeling are valuable tools for simulation, characterization and testing of fast ULSI circuits.

A new "critical-current at linear-threshold" method for direct extraction of deep-submicron MOSFET effective channel length

A novel method for direct extraction of deep-submicron MOSFET effective channel length is proposed, which requires only a single measurement of the "critical-current at linear-threshold" ("I/sub crit/@V/sub t0/") based on the maximum-g/sub m/ definition. With a simple calibration of the channel sheet resistance from the long-channel I/sub crit/ data, the effective channel length of any short-channel device on the same wafer can be determined with one measurement of I/sub crit/@V/sub t0/. Meanwhile, an averaged (modeled) effective channel length can be obtained from the same data set with a simple algorithm, which can be used for device/circuit modeling.

An effective channel length determination method for LDD MOSFETs

We propose a definition of MOSFET effective channel length (L/sub EFF/), that provides a method of determining L/sub EFF/ as a constant, and external resistance (R/sub EXT/) virtually as a constant, even for lightly doped drain (LDD) transistors. A unified relationship between this L/sub EFF/ and MOSFET drive current (linear and saturation) that is common to a wide range of drain structures was confirmed. Therefore, the L/sub EFF/ is useful, not only for compact analytical models, but also as an index of MOSFET performance applicable to both single drain and LDD devices. The dependence of the channel length on the source/drain structure was clarified by introducing the concept of local contribution to channel length. The L/sub EFF/ varies, even if the metallurgical channel length is fixed, depending on the design of the source/drain.

SOI MOSFET effective channel mobility

The standard bulk MOSFET definition for effective electric field is modified for SOI devices to account for nonzero electric field at the back oxide interface. The effective channel mobility in fully-depleted n-channel SOI MOSFET's is shown to be independent of applied backgate bias when the modified E/sub eff/ definition is used. The effective channel mobility as a function of E/sub eff/ is also shown to be independent of film thickness for fully-depleted devices. >

MOSFET effective channel width determination by nonlinear optimization

Accurate determination of MOSFET effective channel width W eff is important for process control and device design. Existing methods to determine W eff are sensitive to measurement noise, and to nonlinearities in the data. In this paper we present a new method to determine W eff that overcomes these problems. The method uses nonlinear optimization, and is based on a drain current model that accounts for the variations of W eff, of series resistance, and of threshold voltage, with masked channel width and gate bias. We also show that our new method is more accurate and less sensitive to measurement procedure than other methods.

Delay prediction from resistance-capacitance models of general MOS circuits

Most existing techniques for computing the delay in linear resistance-capacitance (RC) networks will yield inaccurate results when applied to MOS transistor circuits, because they do not provide a means for determining the MOSFET's effective channel resistance, which is a function of the capacitive load. The iterative method, in which the RC network is converted to a tree by node splitting is an exception. An efficient algorithm which takes the above dependence into account by adjusting the resistances in the model within the iterative process of the LM algorithm is presented. It is shown that by focusing on high-capacitance nodes and by distributing the split capacitances on the basis of path conductances, it is possible in many cases to dispense with iteration. For large transistor groups, decomposition into biconnected components is shown to be very effective. Combinations of these techniques have been tested on a large variety of circuits, a representative subset of which is presented.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

MOSFET effective channel length, threshold voltage, and series resistance determination by robust optimization

MOSFET parameters, such as effective channel length, series resistance, and channel mobility, are important for process control and device design. These parameters are typically obtained from intercepts and slopes of plots of intermediate quantities, such as peak transconductance, derived from I-V data. Commonly, the intercept of a plot is found by extrapolation. However, the extrapolation process is sensitive to measurement errors. In addition, the plots often show nonlinear behavior, hence slopes and intercepts cannot be determined accurately. It is shown how these problems can be overcome by using a nonlinear optimization procedure to determine those MOSFET parameters, by explicitly identifying them as the parameters of a simple, widely used MOSFET model that is a good approximation in the triode region of operation. The results of five tests of robustness and accuracy that show that the method is significantly more accurate and robust than a number of other methods are presented. >

A method to extract gate-bias-dependent MOSFET's effective channel width

A modification to the conventional channel conductance method is introduced to extract the MOSFET's effective channel width W/sub eff/. The gate-bias-dependent effective channel width can be readily delineated with this extraction method. The physical meaning of this gate-bias dependence is further discussed, and structures with different isolation configurations are studied. W/sub eff/ is influenced by the local oxide thickness, surface doping concentration, and gate voltage. Unless the transition between the channel active area and field isolation area is so abrupt that changes of both oxide thickness and doping concentration are like step functions, gate-bias dependence of W/sub eff/ will be inevitable. As gate bias increases in the strong inversion region larger gate bias will gradually turn on the transition region. This in turn increases the W/sub eff/. A strong or weak gate-voltage dependence of W/sub eff/ is indicative to a gradual or fast transition in doping concentration and oxide thickness from channel to the field regions.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A new method to determine the MOSFET effective channel width

A method of determining the effective channel width of a MOSFET device that is simple and accurate is discussed. While simple, this method takes the width-dependent series resistance of MOSFETs into account, which has not been done in previous methods. The results correlate well with SEM cross section measurements. In addition, the method is applicable to current scaled MOSFETs, requiring no measurements outside the normal operating range of the devices being characterized.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Improved statistical method for extraction of MOSFET effective channel length and resistance

The standard electrical method for the extraction of the effective channel length and external resistance of a MOSFET, based upon regression analysis of resistance data, is found to underestimate the variability of these parameters. This was found using statistical experimentation on the method in which various error components were simulated using a Gaussian random-number generator. The problem with the standard method is that it tends to suppress the device-to-device variability inherent in the data and gives confidence intervals that are too narrow and too optimistic. Two alternative methods for data analysis are presented that alleviate this problem: a multiple regression performed on a transformed set of data variables, and an iterative method. Using either of the methods, it is shown that the accuracy of the extracted effective channel length is only as good as the accuracy with which the mask lengths are specified. It is possible, however, to detect the presence of these errors after a data transformation.

A derivative method to determine a MOSFET's effective channel length and width electrically

A new method is presented to determine the channel-width reduction ΔW and the channel-length reduction ΔL in CMOS transistors. By measuring the transconductance of certain sets of n-channel and p-channel MOSFET's biased at low gate and drain voltages in the linear region, a set of derived first-order linear equations is used iteratively to solve for ΔW and ΔL. The results agree with the process observations of fabricated CMOS devices.