Chain Test Structures Research Articles

Electrical Demonstration of TSV Interconnects and Multilevel Metallization for 3D Si Interposer Applications

A TSV test vehicle lot and 3D interposer demonstration lot were successfully fabricated and tested. Fabrication of the TSV test vehicle was accomplished using three process (mask) levels – front-side metal, backside TSV, and backside metal. The TSVs were formed using a vias-last approach with a nominal TSV size of 100μm, and an aspect ratio of 6:1. DRIE bottom clear process conditions were tested which produced 100 % yield on TSV contact chains with up to 540 vias. In addition, optimum process conditions resulted in a TSV resistance of 29 mΩ, and sufficient TSV isolation resistance (> 1MΩ) for the target application. The interposer demonstration lot incorporated five front-side metal levels, one TSV level, and two backside metal levels. The first four metal layers (M1-M4), utilized 2μm Cu and 2μm oxide layers. Metal layers M2-M4 were fabricated using a self-aligned dual damascene process. Each wafer in the demonstration lot had 4 MLM contact chain test structures, with 26400 vias per structure. On two wafers, 100 % yield was achieved on the MLM contact chains. For the dual damascene levels, average contact resistance per via was 4 mΩ. Functional testing was performed on two die from the demonstration lot (die size = 4 cm X 3.7 cm). Over 99 % of the functional nets (circuit paths) passed. Yield on large area test capacitors, tested at wafer level, exceeded 80 %.

Fabrication and characterization of metal-to-metal interconnect structures for 3-D integration

The use of collapsible (solder) bump interconnects in pixel detector hybridization has been shown to be very successful. However, as pixel sizes decrease, the use of non-collapsible metal-to-metal bump bonding methods is needed to push the interconnect dimensions smaller. Furthermore, these interconnects are compatible with 3D intgration technologies which are being considered to increase overall pixel and system performance. These metal-to-metal bonding structures provide robust mechanical and electrical connections and allow for a dramatic increase in pixel density. Of particular interest are Cu-Cu thermocompression bonding and Cu/Sn-Cu solid-liquid diffusion bonding processes.Working with Fermilab, RTI undertook a demonstration to show that these bump structures could be reliably used to interconnect devices designed with 20 micron I/O pitch. Cu and Cu/Sn bump fabrication processes were developed to provide a well-controlled surface topography necessary for the formation of low resistance, high yielding, and reliable interconnects. The electrical resistance and yield has been quantified based on electrical measurements of daisy chain test structures and the mechanical strength of the bonding has been quantified through die shear testing. The reliability has been characterized through studies of the impact of thermal exposure on the mechanical performance of the bonds. Cross-section SEM analysis, coupled with high resolution energy dispersive spectroscopy, has provided insight into the physical and chemical nature of the bonding interfaces and aided in the evaluation of the long-term stability of the bonds.

Test Structures for the Characterization of MEMS and CMOS Integration Technology

Test structures have been used to study the feasibility of bonding MEMS to CMOS wafers to create an integrated system. This involves bonding of prefabricated wafers and creating interconnects between the bonded wafers. Bonding of prefabricated wafers has been demonstrated using a chemical-mechanical polishing enabled surface planarization process and an oxygen plasma assisted low temperature wafer bonding process. Two interwafer connection approaches have been evaluated. For an oxide bonding approach, interconnects between wafers are established through contact vias, using a standard multilevel metallization process after the wafer bonding process. Resistances of 3.8-5.2 Omega have been obtained from via chain test structures and an average specific contact resistivity of 1.7 X 10-8 Omega cm2, measured from the single via Kelvin structures. For a direct metal contact approach, electrical connections have been achieved during the bonding anneal stage due to stress relief of the aluminium film.

Redistribution of pads on a singulated IC die using laser direct-write ablation

The use of laser direct-write technology is demonstrated for rapid turnaround redistribution of pads on known good integrated circuit dice. The technology, which is suitable for rapid prototyping of advanced electronic packages, employs an automated laser ablation system with wavelength at 355nm to pattern thin copper films to form the interconnect and vias in the polyimide interlevel insulator. The ablation tool is designed to directly accept the CAD data and write the metallization and via level patterns with excellent (/spl plusmn/3/spl mu/m) layer-to-layer registration. This process is maskless and, except for cleaning steps, does not require patterning by wet chemical etching. The implementation of a change in the design can be done rapidly and involves modifying the CAD data, downloading it to the laser ablation tool, and fabricating a part according to the new design. This paper illustrates the use of laser direct-write ablation for fabrication of via chain test structures and redistribution of pads on functional integrated circuits on singulated dice. Comparable electrical test results were obtained between structures fabricated using laser ablation technology and those fabricated on full 150-mm diameter wafers using conventional photolithography and etch processes.

200-mm wafer-scale transfer of 0.18-/spl mu/m dual-damascene Cu/SiO/sub 2/ interconnection system to plastic substrates

We report a low-temperature (<200/spl deg/C) 200-mm wafer-scale transfer of a 0.18-/spl mu/m dual-damascene Cu/SiO/sub 2/ interconnection system to FR-4 plastic substrates using adhesive bonding. We demonstrate removal of the silicon bulk layer to leave behind a flexible 3-/spl mu/m-thick Si back-end-of-line (BEOL) circuit on a 0.1-mm-thick FR-4 wafer. The mechanical and electrical integrity of the thin Si BEOL circuit on FR-4 are confirmed by focused ion beam scanning electron microscope microscopy and current-voltage characterization on a variety of test structures, which include serpentine, via chain and Kelvin test structures on different locations on the wafer. This process will pave the path to allow integration of high-performance submicrometer Si electronics on plastic substrates.

200 mm wafer-scale substrate transfer of 0.13μmCu∕low-k (Black Diamond™) dual-damascene interconnection to glass substrates

We report a low-temperature (350 °C) pulsed-voltage anodic bonding followed by grind/etch-back method for 200 mm wafer-scale substrate transfer of 0.13μmCu∕low-k (Black Diamond™) dual-damascene interconnection to glass substrates. Standard back-end-of-line (BEOL) 3kÅSiN∕3kÅ undoped Si glass passivating films were used as buffer layers between donor wafer and glass wafer to facilitate the bonding. We demonstrate removal of the silicon bulk layer to leave behind a transparent (∼1.25μm thick) 0.13μm BEOL circuit on a 1-mm-thick glass wafer. The quality of the mechanical and electrical integrity of the deep submicron BEOL circuit is confirmed by focused ion beam-scanning electron microscopy microscopy and I-V characterization on via chain test structures. This technique has potential applications for bioelectronics and optoelectronics integration schemes.

Physical failure analysis in semiconductor industry—challenges of the copper interconnect process

Since the copper interconnect dimensions shrunk continuously, physical failure analysis becomes increasingly important for process optimization. Failure localization and defect analysis in interconnect structures as well as analysis of barrier/seed step coverage are challenges of the copper inlaid technology. Failure localization in via chain test structures using voltage contrast analysis with SEM/FIB tools and OBIRCH and subsequent destructive failure analysis using FIB/SEM and TEM are described. The inspections of voids in copper interconnects and of buried residuals in vias are typical tasks for process monitoring, which make the application of leading-edge analytical techniques necessary. Barrier/seed step coverage analysis at via chains challenges both TEM sample preparation and analysis. 3D object reconstruction by electron tomography is a promising future method for this task.