Test Structures for the Characterization of MEMS and CMOS Integration Technology

Abstract

Test structures have been used to study the feasibility of bonding MEMS to CMOS wafers to create an integrated system. This involves bonding of prefabricated wafers and creating interconnects between the bonded wafers. Bonding of prefabricated wafers has been demonstrated using a chemical-mechanical polishing enabled surface planarization process and an oxygen plasma assisted low temperature wafer bonding process. Two interwafer connection approaches have been evaluated. For an oxide bonding approach, interconnects between wafers are established through contact vias, using a standard multilevel metallization process after the wafer bonding process. Resistances of 3.8-5.2 Omega have been obtained from via chain test structures and an average specific contact resistivity of 1.7 X 10-8 Omega cm2, measured from the single via Kelvin structures. For a direct metal contact approach, electrical connections have been achieved during the bonding anneal stage due to stress relief of the aluminium film.