Divider Chain Research Articles

Design of synchronous frequency dividers in 5‐nm FinFET CMOS technology

AbstractA method is presented for the design of high‐speed frequency dividers in which the divided output signals are phase aligned by means of a scheme based on cascaded retiming. The objective of the design method proposed is to break the accumulation of propagation delay occurring in a divider chain that may limit the speed of the phase synchronization. Compared to alternative approaches where the phase synchronization is achieved with additional logical gates applied to the divider outputs, the authors’ approach only uses latches that are identical to those already employed in the divider chain itself without any additional synchronization logic. Hence, a better uniformity and homogeneity of the layout can be achieved, which helps improve the phase balancing. The method proposed to design synchronous dividers has been implemented in 5‐nm FinFET CMOS technology by means of a synchronous 8b‐counter providing the division factors 1/2 through 1/256. Its output phase synchronization has been verified in measurements at 10 GHz. The measured power consumption is 720 μW and the silicon area of the divider implemented is 79 μm2.

A Q-Band CMOS Image-Rejection Receiver Integrated with LO and Frequency Dividers

This paper presents a Q-band image-rejection receiver using a 65 nm CMOS technology. For a high image-rejection ratio (IMRR), the Q-band receiver employs the Hartley architecture which consists of a Q-band low-noise amplifier, two down-conversion mixers, a 90° hybrid coupler, and two IF baluns. In addition, a Q-band fundamental voltage-controlled oscillator (VCO) and a frequency divider chain divided by 256 are integrated into the receiver for LO. A charge injection technique is employed in the mixers to reduce the DC power while maintaining a high conversion gain and linearity. The VCO adopts a cross-coupled topology to secure stable oscillation with high output power in the Q-band. The frequency divider chain is composed of an injection-locked frequency divider (ILFD) and a multi-stage current-mode logic (CML) divider to achieve a high division ratio of 256, which facilitates the LO signal locking to an external phase-locked loop. An inductive peaking is employed in the ILFD to widen the locking range. The Q-band image-rejection receiver exhibits a peak conversion gain of 16.4 dB at 43 GHz. The IMRR is no less than 35.6 dBc at the IF frequencies from 1.5 to 5 GHz.

A 5.42~6.28 GHz Type-II PLL with Dead-Zone Programmability and Charge Pump Mismatch Trimming

This paper proposed a 5.42~6.28 GHz type-II phase locked loop (PLL) for the sake of both loop filter switching capability and extensive programmability. An on-chip loop filter is used in conjunction with off-chip one to form a switching filter pair for diverse application scenarios. In order to strike a balance between dead-zone elimination and noise contribution minimization, a 3-bit programmable reset time ranging from 25 ps to 200 ps with a step of 25 ps is brought into PFD (phase frequency detector) design while CP (charge pump) current is programmable from 200 μA to 900 μA with a 100 μA/step digital control. Power management units (PMU) including bandgap and low dropout regulators (LDO) are integrated on-chip with resistor string trimming which effectively counteracts fabrication variations. In addition, a piecewise linear VCO with 3-bit control is designed with a fully digital 6-bit multi-modulus divider (MMD) chain cascaded. The proposed PLL is implemented in a 40-nm bulk CMOS process and the power consumption is 8 mA@1.2 V, in which around 5 mA@1.2 V is consumed by output buffers. The fabricated PLL chip achieves a frequency tuning range of 5.42~6.28 GHz, a phase noise ranging from −107.2~−110.4 dBc/Hz@1 MHz offset from carrier, a reference spur of lower than −70 dBc when on-chip active loop filter bandwidth is set to be around 500 KHz. Its FoM is approximately −176.98~−180.18 dBc/Hz while FoMT is approximately −180.32~−183.52 dBc/Hz@1 MHz offset from carrier. Its most specifications are comparable to or better than most existing literature.

An 8-Gbps, Low-Jitter, Four-Channel Transmitter with a Fractional-Spaced Feed-Forward Equalizer

An 8 gigabits per second (Gbps), low-jitter, four-channel transmitter with fractional-spaced feed-forward equalizer (FFE) is designed to meet the demand for broad transmission bandwidth in serial data communications. A novel frequency divider chain (FDC) architecture is developed, to satisfy the time requirements for high-speed data serialization. Moreover, a reconfigurable output driver circuit is employed to ensure compatibility with different protocols. In addition, a three-tap fractional-spaced FFE, which can enhance signal bandwidth significantly, is proposed, to compensate for channel loss. The transmitter was simulated and validated based on the Semiconductor Manufacturing International Corporation (SMIC) 55-nm process. The post-layout simulation results show the following: The tuning range of the phase-locked loop (PLL) can cover 1.6 to 4.6 GHz. At an output frequency of 4 GHz, the root-mean-square jitter (RJ) of the PLL after integration from phase noise was 1.93 ps. With an 8 Gbps output data rate, using the pseudo-random binary sequence (PRBS)-31 as a data source to simulate the whole transmitter, the power consumption values of the PLL and drive circuit were 27.0 and 29.2 mW, respectively, and the eye width and the valid eye height of output data were 0.76 unit interval (UI) and 0.68.

A 78.8-84 GHz Phase Locked Loop Synthesizer for a W-Band Frequency-Hopping FMCW Radar Transceiver in 65 nm CMOS.

A W-band integer-N phase-locked loop (PLL) for a frequency hopping frequency modulation continuous wave (FMCW) radar is implemented in 65-nm CMOS technology. The cross-coupled voltage-controlled oscillator (VCO) was designed based on a systematic analysis of the VCO combined with its push-pull buffer to achieve high efficiency and high output power. To provide a frequency hopping functionality without any overhead in the implementation, the center frequency of the VCO is steeply controlled by the gate voltage of the buffer, which effectively modifies the susceptance of the VCO load. A stand-alone VCO with the proposed architecture is fabricated, and it achieves an output power of 13.5 dBm, a peak power efficiency of 9.6%, and a tuning range of 3.5%. The phase noise performance of the VCO is −92.6 dBc/Hz at 1-MHz and −106.1 dBc/Hz at 10 MHz offset. Consisting of a third-order loop filter and a divider chain with a total modulus of 48, the locking range of the implemented PLL with the cross-coupled VCO is recorded from 78.84 GHz to 84 GHz, and its phase noise is −85.2 dBc/Hz at 1-MHz offset.

40 GHz VCO and Frequency Divider in 28 nm FD-SOI CMOS Technology for Automotive Radar Sensors

This paper presents a 40 GHz voltage-controlled oscillator (VCO) and frequency divider chain fabricated in STMicroelectronics 28 nm ultrathin body and box (UTBB) fully depleted silicon-on-insulator (FD-SOI) complementary metal-oxide–semiconductor (CMOS) process with eight metal layers back-end-of-line (BEOL) option. VCOs architecture is based on an LC-tank with p-type metal-oxide–semiconductor (PMOS) cross-coupled transistors. VCOs exhibit a tuning range (TR) of 3.5 GHz by exploiting two continuous frequency tuning bands selectable via a single control bit. The measured phase noise (PN) at 38 GHz carrier frequency is −94.3 and −118 dBc/Hz at 1 and 10 MHz frequency offset, respectively. The high-frequency dividers, from 40 to 5 GHz, are made using three static CMOS current-mode logic (CML) Master-Slave D-type Flip-Flop stages. The whole divider factor is 2048. A CMOS toggle flip-flop architecture working at 5 GHz was adopted for low frequency dividers. The power dissipation of the VCO core and frequency divider chain are 18 and 27.8 mW from 1.8 and 1 V supply voltages, respectively. Circuit functionality and performance were proved at three junction temperatures (i.e., −40, 25, and 125 °C) using a thermal chamber.

A 125 GHz millimeter-wave phase lock loop with improved VCO and injection-locked frequency divider in 65 nm CMOS process

In this paper, a CMOS mm-wave phase locked loop (PLL) with improved voltage controlled oscillator (VCO) and injection-locked frequency divider (ILFD) at operational harmonic frequency 125 GHz is presented. The VCO structure uses the bulk effective and MOS varactor capacitor to adjust parasitic capacitor of the cross coupled pair. It obtains 2th harmonic frequency with 24% tuning range (110–140 GHz) by applying ± 1.2 V input voltage variation. The divide-by-4 ILFD circuit uses a cross coupled VCO with three injection transistors acting in linear and nonlinear regions. The frequency dividers such as divided-by-4 ILFD, subsequent current mode logic (CML) and true single phase clock (TSPC) as divider chain with ratio 1/256 are used to synthesize frequency 244 MHz which is compared to reference frequency, 244 MHz in the PLL. Simulation results of the proposed PLL circuit are obtained after extracting post layout (with total chip size of 0.29 mm2) in 65 nm CMOS standard technology and @ 1.2 V power supply voltage. The obtained results confirm theoretical relations and indicate that the proposed circuit has good figure of merit (FoM), and higher tuning range and lower die area than the recent designs.

A V-Band Phase-Locked Loop with a Novel Phase-Frequency Detector in 65 nm CMOS

A 65–67 GHz phase-locked loop (PLL) with a novel low power phase-frequency detector (PFD) in 65 nm LP CMOS is presented. The PLL consists of a V-band voltage-controlled oscillator (VCO), a divide-by-two injection-locked frequency divider (ILFD), and a current-mode logic (CML) divider chain. A charge pump (CP) and a 2nd-order loop filter are used with PFD for VCO tuning. The PFD is implemented with 16 transistors with dead-zone-free capability. The measured locking range of the PLL is from 65.15 to 67.4 GHz, with −11.5 dBm measured output power at 66.05 GHz while consuming 88 mW. The measured phase noise at 1 MHz offset is −84.43 dBc/Hz. The chip area of the PLL is 0.84 mm2 including probing pads. The proposed PLL can be utilized as a frequency synthesizer for carrier signal generation in IEEE 802.11ad standard high data rate transceiver circuits.

A 210–284-GHz I–Q Receiver With On-Chip VCO and Divider Chain

A 240-GHz direct conversion I–Q receiver with 74-GHz RF bandwidth is reported. It features a mixer-first architecture with fundamental local oscillator (LO)-frequency Gilbert-cell downconversion mixers, variable-gain baseband amplifiers, and a 240-GHz LO source, making it the first fully integrated 240-GHz I–Q receiver. With a phase noise of −82 dBc/Hz at 1-MHz offset, the LO source has a 27-GHz tuning range and consists of a 120-GHz voltage-controlled oscillator (VCO), a frequency doubler, and a static divide-by-128 chain. The measured peak downconversion gain is 23 dB and is adjustable over 38 dB. Along with the IF bandwidth of 59 GHz, the wide RF bandwidth makes it suitable for both high data-rate communication and emerging quantum computing applications. The chip occupies an area of 1.837 mm2 and consumes 859 mW.

0.1–5 GHz wideband ΔΣ fractional‐N frequency synthesiser for software‐defined radio application

This article proposes a wideband ΔΣ fractional-N frequency synthesiser (WBFS) for software-defined radio application. The frequency synthesiser has two modes: the regular mode with low phase noise performance and the low-power mode for the low-power applications at lower frequency band. The authors also propose adjustable replica (AR) bias circuit for the frequency selection multiplexer (FSMUX) in the divide-by-two divider chain to optimise the power consumption at different frequencies while keep the output swing constant at different bias current to achieve robust operation. The FSMUX is implemented in differential structure instead of the widely used quadrature structure to reduce power and area especially at high carrier frequency. Implemented in 65 nm CMOS process with a 1.2-V supply, the WBFS generates frequency from 0.1 to 5 GHz. The maximum power at regular and low-power mode is 21 and 10.2 mW, respectively. The phase noise is −120.3 dBc/Hz at 1 MHz offset (2.75375 GHz) at regular mode and −122.8 dBc/Hz at 1 MHz offset (1.3525 GHz) at low-power mode. Thanks to the differential FSMUX with the proposed AR bias circuit and the low-power mode, the WBFS power is significantly reduced, compared with that of the prior WBFS with comparable frequency range.

Microwave Synthesis for the PTB Cesium Fountain Clocks

Microwave synthesizers that are used to generate microwave signals for the CSF1 and CSF2 fountain clocks at the Physikalisch-Technische Bundesanstalt (PTB) are described. The synthesizers are based on a divider chain and a digital frequency synthesis and have been designed for use with an optically stabilized microwave oscillator. They have been designed in a modular fashion to assure long-term operation and low down times. The results of an in-depth examination of spectral purity, phase noise, and long-term phase stability are presented. Also, the implications of measured parameters on the fountain timing are assessed. Two methods of suppressing the frequency-shifting effect of microwave leakage fields are implemented, with one method in each synthesizer. The first method uses an interferometric switch, and the second uses a phase-coherent and phase-preserving frequency detuning scheme; their contribution to the systematic uncertainty of the fountains is assessed. The overall systematic uncertainty contribution associated with the fountain electronics is below $1 \times 10^{-17}$ for both fountain clocks.

10-15 Frequency Stability Microwave Synthesizer for Atomic Fountain Frequency Standard

This paper presents the design and phase noise measurement of microwave frequency synthesizer for atomic fountain frequency standard. In this synthesizer, a voltage-controlled DRO is locked to 100MHz hydrogen maser signal through a divider chain. The required interrogation frequency 9192631770 Hz is generated by mixed with 7368230 Hz and 400 MHz signals. The experimental results show that the phase noise of interrogation signal at 9.192 GHz is -88dBc/Hz@ offset 1Hz. With such performances, the expected Dick effect contribution to atom fountain frequency standard is reported at a level of 1.0×10-15 at 1 s integrating time, that is a factor 10 higher than quantum noise limit of atom frequency standard. The carrier spectral spur of microwave synthesizer signal impacted on atomic fountain frequency standard is also discussed.

A compact 0.045–2.3 GHz frequency synthesizer with a wide tuning range low phase noise VCO for software defined radios

A compact 0.045–2.3 GHz wideband fractional-N frequency synthesizer (FS) for software defined radios (SDR) applications is presented in this paper. Based on a single phase locked loop (PLL) that employs one integrated inductor-capacitor voltage controlled oscillator (VCO), the proposed FS can provide a wide operating frequency range. The VCO adopts an optimized circular inductor to mitigate the phase noise degradation caused by the high VCO gain. The in-band phase noise is optimized by employing current mode logic dividers and true single phase clock dividers. The PLL provides the differential outputs ranging from 2.3 to 4.6 GHz and the 0.045–2.3 GHz quadrature local oscillator signals are generated by the following divider chain. The proposed FS is implemented in TSMC 180 nm RFCMOS process and provides a phase noise performance less than − 116 dBc/Hz at 1 MHz offset. The maximum power consumption is 54 mW. The die size including pads and I/O is 1.92 mm2 with an active core area of 1.13 mm2. This proposed circuit has the great potential for SDR applications.

A 283-GHz Fully Integrated Phase-Locked Loop Based on 65-nm CMOS

A 283-GHz fully integrated phase-locked loop (PLL) based on a 65-nm CMOS technology is presented. A triple-push ring voltage-controlled oscillator and a frequency divider chain (/16,384) composed of 2 injection-locked frequency dividers are developed, which are integrated with 12 current-mode logic frequency dividers, a phase frequency detector, a charge pump, and a loop filter. The fabricated PLL showed a locking range of 282.3–283.7 GHz and a phase noise of −53.5 dBc/Hz at 100 kHz (in band) and −78.6 dBc/Hz at 10 MHz (out of band). Total dc power consumption is 114 mW. The chip occupies 920 × 520 μ m2 excluding probing pads.

A monolithic K-band phase-locked loop for microwave radar application**Project supported by the National High-Tech Research and Development Program of China (No. 2013AA014101).

A monolithic K-band phase-locked loop (PLL) for microwave radar application is proposed and implemented in this paper. By eliminating the tail transistor and using optimized high-Q LC-tank, the proposed voltage-controlled oscillator (VCO) achieves a tuning range of 18.4 to 23.3 GHz and reduced phase noise. Two cascaded current-mode logic (CML) divide-by-two frequency prescalers are implemented to bridge the frequency gap, in which inductor peaking technique is used in the first stage to further boost allowable input frequency. Six-stage TSPC divider chain is used to provide programmable division ratio from 64 to 127, and a second-order passive loop filter with 825 kHz bandwidth is also integrated on-chip to minimize required external components. The proposed PLL needs only approximately 18.2 μs settling time, and achieves a wide tuning range from 18.4 to 23.3 GHz, with a typical output power of −0.84 dBm and phase noise of −91.92 dBc/Hz @ 1 MHz. The chip is implemented in TSMC 65 nm CMOS process, and occupies an area of 0.56 mm2 without pads under a 1.2 V single voltage supply.

A 6‐GHz spread spectrum clock generation with EMI reduction of 30.2 dB for SATA‐III applications

ABSTRACTIn this letter, a 6‐GHz spread spectrum clock generation for Serial AT Attachment Generation 3 (SATA—III) applications in 0.18‐pm CMOS technology is presented. The 3rd‐order loop filter is to reduce the ripple of control voltage of VCO and the loop bandwidth is 625 KHz. With the aid of second‐order delta‐sigma (ΔΣ) modulator and triangular profile counter, the division ratio of divider chain can be changed periodically. The modulation frequency is 37.04 KHz with upper bound of 19 for the triangular profile counter. The proposed circuit spreads 30‐MHz frequency range from 5.97 to 6.0 GHz with an EMI reduction of 20.3 dB. The dc power consumption is 34 mW with a chip size of 0.54 mm2. © 2017 Wiley Periodicals, Inc. Microwave Opt Technol Lett 59:622–624, 2017

A 0.56 THz Phase-Locked Frequency Synthesizer in 65 nm CMOS Technology

This paper presents the design and characterization of a 0.56 THz frequency synthesizer implemented in standard 65 nm CMOS technology. Its front end consists of triple-push Colpitts oscillators (TPCOs), followed by the first and second stage injection locking frequency dividers (ILFDs) and a divide-by-16 chain. TPCOs are used to triple their fundamental frequencies to 0.53–0.56 THz, while ILFDs and the subsequent divider chain are used to divide such frequencies to 2.7–2.9 GHz. Its back end consists of separate frequency and phase-locked loops with unique CMOS circuit designs to accomplish the desirable frequency/phase locking, including: 1) band-selection inductor switches; 2) simultaneous bulk voltage tuning over TPCOs and the first ILFD; and 3) a dual port injection architecture for the first ILFD. The resultant prototype realizes a 21 GHz frequency locking range with phase noise lower than −74 dBc/Hz at 1 MHz offset, and consumes 174 mW dc power.

A fully integrated CMOS 60-GHz transceiver for IEEE802.11ad applications

A fully integrated 60-GHz transceiver for 802.11ad applications with superior performance in a 90-nm CMOS process versus prior arts is proposed and real based on a field-circuit co-design methodology. The reported transceiver monolithically integrates a receiver, transmitter, PLL(Phase-Locked Loop) synthesizer, and LO (Local Oscillator) path based on a sliding-IF architecture. The transceiver supports up to a 16QAM modulation scheme and a data rate of 6 Gbit/s per channel, with an EVM (Error Vector Magnitude) of lower than −20 dB. The receiver path achieves a configurable conversion gain of 36∼64 dB and a noise figure of 7.1 dB over 57∼64 GHz, while consuming only 177 mW of power. The transmitter achieves a conversion gain of roughly 26 dB, with an output P1dB of 8 dBm and a saturated output power of over 10 dBm, consuming 252 mW of power from a 1.2-V supply. The LO path is composed of a 24-GHz PLL, doubler, and a divider chain, as well as an LO distribution network. In closed-loop operation mode, the PLL exhibits an integrated phase error of 3.3° rms (from 100 kHz to 100 MHz) over prescribed frequency bands, and a total power dissipation of only 26 mW. All measured results are rigorously loyal to the simulation.

A 5 GHz fully-integrated low-power phase-locked loop using 0.18-μm CMOS technology

A 5 GHz fully integrated low-power phase-locked loop (PLL) was designed and fabricated on 0.18-μm CMOS process. To achieve low power consumption, the transformer feedback VCO and high speed true single phase clock (TSPC) divider were adopted. A rail-to-rail buffer amplifier was incorporated between the VCO and TSPC divider chain to provide full voltage swing for TSPC input. In addition, dual varactor pairs were utilized to enlarge the tuning rage of the VCO while maintaining the low KVCO. The PLL achieved low power of 12.12 mW with good phase noise. The closed loop phase noises were −90.88 and −115.8 dBc/Hz at 100 kHz and 10 MHz frequency offsets. © 2016 Wiley Periodicals, Inc. Microwave Opt Technol Lett 58:1534–1537, 2016

A W-Band 4-GHz Bandwidth Phase-Modulated Pulse Compression Radar Transmitter in 65-nm CMOS

This paper presents a fully integrated W-band 4-GHz bandwidth (BW) pseudo-noise (PN)-coded pulse compression radar transmitter (TX) in a CMOS technology. The PN-coded pulse compression scheme is adopted to obtain high spectral density and to lower the TX leakage using a 63-bit PN code generator based on linear feedback shift registers. We propose a sub-harmonic pumped pulse former and a pulsed power amplifier for high TX efficiency with the suppression of local oscillator (LO)/2LO leakage. A frequency synthesizer including a frequency divider chain generates a sub-harmonic LO signal, as well as a 5-GHz digital clock. Digital blocks with the PN-code generator are synchronized with the clock signal, which makes all pulses start with the same phase. The proposed TX achieves 14.5-dBm maximum output power with the tuning range of 75–81.5 GHz, and the phase noise is ${-}{\hbox{95.2}}$ dBc/Hz at a 1-MHz offset in the range of LO frequencies. In pulse mode, it generates a 4-GHz BW RF pulse signal, which corresponds to a range resolution of 7.5 cm, and the average dc power dissipation is 160 mW.