Ceramic Column Grid Array Package Research Articles

Study on Vibration and Thermal Characteristics Applying Staking to CCGA Package for Space Applications

This paper describes the stacking effect for Ceramic Column Grid Array(CCGA) packages used for satellites. Reflow Soldering Process suitable for CCGA package with back structure was set as the process development goal to meet European Cooperation for Space Standardization(ECSS) standard. After analyzing the stacking effect according to the type of CCGA, it is verified by applying it to the CCGA Reflow Soldering Process. In order to confirm the validity of the staking effect analyzed in terms of vibration and thermal characteristics, it is verified through actual specimen production. It analyzes the cause of crack occurrence in the CCGA package and estimates the crack generation point using previously acquired inspection data. Keywords: Corner Staking, CCGA Package, Reflow Soldering Process, Crack, Vibration

Solder Immersion Process of Ceramic Column Grid Array Package Assembly for Space Applications

Ceramic column grid array (CCGA) packages are progressively being utilized for logic and microprocessor functionalities requiring very high-density interconnections. These packages offer various advantages, such as high reliability, good thermal and electrical performance, and reduced size and weight, due to which the use of these packages in space applications is becoming more and more popular. Assembly of such packages is always challenging for assembly and quality assurance engineers due to its post assembly inspection and rework limitations. These packages are usually assembled using the standard surface-mount technology (SMT) assembly processes involving solder paste printing on printed circuit boards (PCBs), component placement, and reflow soldering. An innovative tweak to the SMT process named solder immersion process (SImP) for assembly of CCGA is invented, where the solder paste is applied on the columns of the CCGA packages replacing the conventional solder paste printing/dispensing. SImP is useful for prototyping and reworkability and results in substantial improvement of the solder joint quality. This article explains the SImP in detail, test vehicle preparation, quality evaluation and subsequent accelerated thermal cycling test results, its applications, and advantages in the field of prototyping and reworkability.

Reliability of Ceramic Column Grid Array (CCGA717) Interconnect Packages Under Extreme Temperatures for Space Applications*

Ceramic column grid array packages have been increasing in use based on their advantages such as high interconnect density, very good thermal and electrical performance, compatibility with standard surface-mount packaging assembly processes, and so on. CCGA packages are used in space applications such as in logic and microprocessor functions, telecommunications, flight avionics, and payload electronics. As these packages tend to have less solder joint strain relief than leaded packages, the reliability of CCGA packages is very important for short-term and long-term space missions. CCGA interconnect electronic package printed wiring boards (PWBs) of polyimide have been assembled, inspected nondestructively, and subsequently subjected to extreme temperature thermal cycling to assess the reliability for future deep space, short- and long-term, extreme temperature missions. In this investigation, the employed temperature range covers from −185°C to +125°C extreme thermal environments. The test hardware consists of two CCGA717 packages with each package divided into four daisy-chained sections, for a total of eight daisy chains to be monitored. The CCGA717 package is 33 mm × 33 mm with a 27 × 27 array of 80%/20% Pb/Sn columns on a 1.27 mm pitch. The resistance of daisy-chained, CCGA interconnects was continuously monitored as a function of thermal cycling. Electrical resistance measurements as a function of thermal cycling are reported and the tests to date have shown significant change in daisy chain resistance as a function of thermal cycling. The change in interconnect resistance becomes more noticeable as the number of thermal cycles increases. This paper will describe the experimental test results of CCGA testing under extreme temperatures. Standard Weibull analysis tools were used to extract the Weibull parameters to understand the CCGA failures. Optical inspection results clearly indicate that the solder joints of columns with the board and the ceramic package have failed as a function of thermal cycling. The first failure was observed at the 137th thermal cycle and 63.2% failures of daisy chains have occurred by about 664 thermal cycles. The shape parameter extracted from the Weibull plot was about 1.47, which indicates the failures were related to failures that occurred during the flat region or useful life region of the standard bathtub curve. Based on this experimental test data, one can use the CCGAs for the temperature range studied for ∼100 thermal cycles (ΔT = 310°C, 5°C/minute, and 15 min dwell) with a high degree of confidence for high reliability space and other applications.

Analysis and Prediction of Vibration-Induced Solder Joint Failure for a Ceramic Column Grid Array Package

Solder joint fatigue failure under vibration loading continues to be a concern in microelectronic industry. Existing literature has not adequately addressed high-cycle fatigue failure of high-lead solder joints, especially under a broad spectrum of vibration frequencies. Also, damage mapping across solder joints in an area-array package has not been effectively studied using numerical models and experimental cross sectioning. This paper aims to develop an experimental and modeling approach that can accurately determine the solder joint behavior of electronic components under vibration conditions. In particular, this paper discusses the out-of-plane sinusoidal vibration experiments at 1G, numerical modeling, and fatigue life prediction for a 42.5×42.5×4mm3 1089 input∕output ceramic column grid array (CCGA) package on a 133×56×2.8mm3 FR4 board. Detailed investigation and characterization involving dye-and-pry analysis, microstructural examination, and numerical modeling enabled the development of a high-cycle stress-based equation for lead-containing CCGA under sinusoidal loading. The developed approach has been applied to a number of cases including a CCGA package with a heat sink as well as a CCGA package subjected to frequency sweeps. It is seen that the predictions from the developed model agree well with experimental data and that the developed model can map the evolution of solder damage across all solder joints and can also provide important design recommendations in terms of solder joint location as well as heat sink attachment.

CCGA packages for space applications

Commercial-off-the-shelf (COTS) area array packaging technologies in high reliability versions are now being considered for applications, including use in a number of NASA electronic systems being utilized for both the Space Shuttle and Mars Rover missions. Indeed, recently a ceramic package version specifically tailored for high reliability applications was used to provide the processing power required for the Spirit and Opportunity Mars Rovers built by NASA-JPL. Both Rovers successfully completed their 3-months mission requirements and continued exploring the Martian surface for many more moths, providing amazing new information on previous environmental conditions of Mars and strong evidence that water exists on Mars. Understanding process, reliability, and quality assurance (QA) indicators for reliability are important for low risk insertion of these newly available packages in high reliability applications. In a previous investigation, thermal cycle test results for a non-functional daisy-chained peripheral ceramic column grid array (CCGA) and its plastic ball grid array (PBGA) version, both having 560 I/Os, were gathered and are presented here. Test results included environmental data for three different thermal cycle regimes (−55/125 °C, −55/100 °C, and −50/75 °C). Detailed information on these—especially failure type for assemblies with high and low solder volumes—are presented. The thermal cycle test procedure followed those recommended by IPC-9701 for tin–lead solder joint assemblies. Its revision A covers guideline thermal cycle requirements for Pb-free solder joints. Key points on this specification are also discussed. In a recent investigation a fully populated CCGA with 717 I/Os was considered for assembly reliability evaluation. The functional package is a field-programmable gate array that has much higher processing power than its previous version. This new package is smaller in dimension, has no interposer, and has a thinner column wrapped with copper for reliability improvement. This paper will also present thermal cycle test results for assemblies of this and its plastic package version with 728 I/Os, both of which were exposed to four different cycle regimes. Two of these cycle profiles are specified by IPC-9701A for tin–lead, namely, −55 to 100 °C and −55 to 125 °C. One is a cycle profile specified by Mil-Std-883, namely, −65/150 °C, generally used for ceramic hybrid packages screening and qualification. The last cycle is in the range of −120 to 85 °C, a representative of electronic systems directly exposed to the Martian environment without use in a thermal control enclosure. Per IPC-9701A, test vehicles were built using daisy chain packages and were continuously monitored and/or manually checked for opens at intervals. The effects of many process and assembly variables—including corner staking commonly used for improving resistance to mechanical loading such as drop and vibration loads—were also considered as part of the test matrix. Optical photomicrographs were taken at various thermal cycle intervals to document damage progress and behavior. Representative samples of these are presented along with cross-sectional photomicrographs at higher magnification taken by scanning electron microscopy (SEM) to determine crack propagation and failure analyses for packages.

Reliability of an 1657CCGA (Ceramic Column Grid Array) Package With 95.5SN3.9AG0.6CU Lead-Free Solder Paste on PCBS (Printed Circuit Boards)

In many applications such as computers and telecommunications, the IC chip sizes are very big, the on-chip frequency and power dissipation are very high, and the number of chip I/Os is very large. The CCGA (ceramic column grid array) package developed by IBM is one of the best candidates for housing these kinds of chips. There are two parts in this study. One is to show that the two-parameter Weibull life distribution is adequate for modeling the thermal-fatigue life of lead-free solder joints. This is demonstrated by comparing the two-parameter and three-parameter Weibull distributions with life test data of an 1657-pin CCGA package with the 95.5 wt %Sn3.9 wt %Ag0.6 wt %Cu lead-free solder paste on lead-free printed circuit boards under thermal cycling conditions. The other part of this study is to determine the time-history creep strain energy density of the 1657-pin CCGA solder column with two different solder paste materials, namely, 95.5 wt %Sn3.9 wt %Ag0.6 wt %Cu and 63 wt %Sn37 wt %Pb and under three different thermal cycling profiles, namely, 25↔75°C, 0↔100°C, and −25↔125°C. The effects of these solder pastes and temperature conditions on the thermal-fatigue life of the high-lead (10 wt %Sn90 wt %Pb) solder columns of the CCGA package are provided and discussed.

Deformation Mechanism of Two-Phase Solder Column Interconnections Under Highly Accelerated Thermal Cycling Condition: An Experimental Study

Thermomechanical behavior of solder interconnections of a ceramic column grid array package assembly is characterized by high sensitivity moire´ interferometry. The in situ thermal deformations of the most distant column from the axis-of-symmetry are documented for (a) an initial isothermal loading of ΔT = −60° and (2) subsequent accelerated thermal cycles of (20°C)−(125°C)−(−40°C)−(20°C). The deformed shape of the column obtained from the displacement fields clearly delineates the effect of the eutectic solder fillet on the column deformation accumulated during accelerated thermal cycling. A deformation mechanism is suggested to explain the results, which is confirmed by the results from the actual accelerated thermal cycle test of the same assembly. The distributions of inelastic strains accumulated during thermal cycles are determined along the sides of the column. The results emphasize the importance of the solder fillet height for optimum reliability. The effect of specimen preparation required for the moire´ experiment on the column deformation is also discussed to validate the experimental data.