Center-tapped Inductor Research Articles

A BL-CC Converter-Based BLDC Motor Drive for Marine Electric Vehicle Applications

This article presents a BLDC (permanent magnet brushless DC) motor drive for marine electric vehicle (MEV) application. The presented scheme uses bridgeless canonical cell (BL-CC) converter with center-tapped inductor (shown as two separate inductors for analysis purpose) for source-side power factor correction (PFC); however, the BL-CC converter requires two inductors. In the presented scheme use of one center-tapped inductor eliminates the requirement of one extra inductor. Thus, center-tapped inductor usage in BLDC motor drive results in decrement in components count. The BL-CC converter-based BLDC motor drive scheme do not require extra back-feeding diodes like other bridgeless (BL) schemes, but it uses inbuilt antiparallel diodes of insulated gate bipolar transistor (IGBT) switches for the same purpose this again leads to decrement in required component count. In this work, PFC BL-CC converter is operated in discontinuous inductor current (DIC) mode to attain better power quality. The DIC mode operation requires only one voltage sensor to sense DC-link voltage, whereas in continuous conduction mode (CCM), the sensor requirement increases to three (two voltage sensors and one current sensor). The PFC BL-CC converter also eliminates the diode bridge rectifier stage. The elimination of one extra inductor, two extra back-feeding diodes, DBR stage and also requirement of only one voltage sensor in DIC mode operation instead of three sensors for CCM implies reduction in components count which implies the reduction in cost and also the volume and weight of the BLDC motor drive. The weight reduction for marine (on-board) electric vehicle is very important as this enhances the vehicle performance. This paper also presents the detailed mathematical modeling and stability analysis of presented BL-CC converter using pole zero map and Bode plot. The BL-CC converter-based BLDC motor driving system for MEV application for DIC mode operation has been developed in the laboratory as well as on MATLAB/Simulink platform and simulated MATLAB and real-time experimental results have been presented to validate the presented BLDC motor drive under steady-state and dynamic operating conditions.

Active Balun with Center-Tapped Inductor and Double-Balanced Gilbert Mixer for GNSS Applications

A new 1.575 GHz active balun with a classic double-balanced Gilbert mixer for global navigation satellite systems is proposed herein. A simple, low-noise amplifier architecture is used with a center-tapped inductor to generate a differential signal equal in amplitude and shifted in phase by 180°. The main advantage of the proposed circuit is that the phase shift between the outputs is always equal to 180°, with an accuracy of ±5°, and the gain difference between the balun outputs does not change by more than 1.5 dB. This phase shift and gain difference between the outputs are also preserved for all process corners, as well as temperature and voltage supply variations. In the balun design, a band calibration system based on a switchable capacitor bank is proposed. The balun and mixer were designed with a 110 nm CMOS process, consuming only a 2.24 mA current from a 1.5 V supply. The measured noise figure and conversion gain of the balun and mixer were, respectively, NF = 7.7 dB and GC = 25.8 dB in the band of interest.

Ultra-High Step-Up DC-DC Converters Based on Center-Tapped Inductors

In this paper, a new family of ultra-high step-up DC-DC converters based on a center-tapped coupled inductor (CI) is proposed. These single-switch converters employ different inductive and capacitive power transfer techniques by utilizing multi-winding CIs, intermediate capacitor links and simple switched-capacitors to improve the transferred power rate, harvest magnetizing and leakage inductance energies, and enhance power density. Achieving high voltage gain in low duty cycle values enables the proposed converters to operate under wide output voltage ranges; meanwhile, distributing the output voltage on two or three output ports alleviates the voltage stress on output terminal components. Low input current ripple, simple pulse width modulation control, low switch voltage stress and operation without circulating current can be listed as other features. In this paper, the proposed family is introduced, theoretically analyzed and compared with other state-of-the-art researches. Finally, the accuracy of analyses are evaluated with some experimental tests of a 1.25 kW experimental prototype.

A comprehensive analysis on differential cross-coupled CMOS LC oscillators via multi-objective optimization

CMOS differential cross-coupled LC oscillators are widely used due to their superior phase noise performance. Even though the number of circuit elements is small, the design process is not trivial due to the complicated trade-off between the phase noise and power consumption. Conventionally, cross-coupled oscillators can be constructed by using only PMOS or only NMOS devices or using both (CMOS). The topology selection is mostly based on either theoretical calculations or experimental (measurement/simulation) results on specific solution points reported in the literature; however, there is no comprehensive analysis on comparison of these topologies in the literature. Also, there are several efforts on improving the phase noise response such as conventional tail noise filtering (using a tail capacitor or LC filter) and sinusoidal tail shaping. Yet, the cost-performance effectiveness of such techniques has not been well-discussed in the literature. In this study, performances of different differential cross-coupled LC oscillators are examined using a parasitic-aware multi-objective RF circuit synthesis tool. PMOS, NMOS, and CMOS types of oscillators were synthesized and performances of those circuits were thoroughly demonstrated. The synthesis results were validated by performing post-layout simulations for different solutions located on the Pareto optimal front (POF). To observe the effect of the other layout parasitics, the CMOS oscillator was also optimized including a parasitic netlist of a drawn layout. The effect of using LC tank with centre-tapped inductor on oscillator performance was also investigated. Furthermore, effectiveness of several phase noise reduction techniques; tail capacitor filtering, tail LC filtering, and sinusoidal noise shaping were demonstrated and discussed in detail.

Modular Multilevel Converter With Magnetically Coupled Branch Inductors

The modular multilevel converter is a well-known modular multilevel topology. This paper proposes a novel branch inductor coupling and compares it to the center-tapped inductor and the standard noncoupled inductor topology. The proposed coupling has a significant influence on the inductor and converter dimensioning. Its properties make it especially well suited for use in single-to-three-phase ac/ac modular multilevel convert-er applications.

A <formula formulatype="inline"><tex Notation="TeX">$K$</tex> </formula>-Band Divide-by-Five Injection-Locked Frequency Divider Using a Near-Threshold VCO

This letter presents a divide-by-five injection-locked frequency divider (ILFD) using a near-threshold (NT) VCO. The input frequency is injected in the proposed ILFD by a VCO employing a noise-cancelling technique. Both the proposed ILFD and VCO are based on a single compact coil which consists of a distributed and center-tapped inductor for an enhanced ILFD locking range of 20.2 to 21.9 GHz without varactors. The proposed VCO and ILFD are fabricated in a 0.13 μm CMOS process and consume 0.3 and 0.55 mW, respectively, from a 0.45 V supply.

A Grid-Level High-Power BTB (Back-To-Back) System Using Modular Multilevel Cascade Converters WithoutCommon DC-Link Capacitor

This paper provides an intensive discussion on analysis, simulation, and experiment of a back-to-back (BTB) system unifying two modular multilevel cascade converters based on double-star chopper cells (MMCCs-DSCCs). Each of the two DSCCs connected back-to-back consists of multiple cascaded chopper cells and a center-tapped inductor per leg. Low voltage steps bring significant reductions in harmonic voltage and current to the BTB system. Neither dc-link capacitor nor voltage sensor is required for regulating the dc-link voltage and controlling the dc-link current. A three-phase 200-V, 10-kW, 50-Hz downscaled BTB system with phase-shifted PWM is designed, constructed, and tested to verify its operating principles and performance. Analytical, simulated, and experimental results agree well with each other in steady and transient states. Experimental waveforms confirm the effectiveness of a self-starting/restarting procedure.

An inductive-degenerated current-bleeding LNA-merged CMOS mixer for 866 MHz RFID reader

This paper presents a new LNA merged mixer topology with improved linearity and noise figure for 866 MHz UHF RFID reader. A novel technique of inductive degeneration of the current bleeding PMOS devices has been utilized to reduce the RF signal leakage through this DC path. This technique along with common-mode inter-modulation feedback and tail capacitance tuning is employed to achieve the superior performance. The mixer was implemented in 130 nm IBM CMOS process and achieved an IIP3 of ?4.1 dBm, a DSB noise figure of 7.5 dB along with a flicker noise 1/f corner frequency of 45 kHz. In addition, with the noise and power matched merged LNA/transconductor, an S11 of ?19.1 dB and an RF-to-IF conversion gain of 17 dB was achieved using a 1.2 V supply. The mixer occupied a silicon area of only 0.54 sq. mm which includes all the center-tapped degeneration and stray tuning inductors.

Discussion on Triangular-Carrier Frequencies of a Modular Multilevel Cascade Converter Based on Double-Star Chopper Cells (MMCC-DSCC) with Phase-Shifted PWM

This paper presents a theoretical discussion on triangular-carrier frequencies of a modular multilevel cascade converter based on double-star chopper cells (MMCC-DSCC, hereafter referred to as the DSCC) with phase-shifted PWM. The DSCC consists of multiple cascaded chopper cells and a center-tapped inductor per leg. Low voltage steps bring significant reductions in harmonic voltage and current to BTB (back-to-back) or HVDC (high-voltage direct-current) systems using two DSCCs. When the DSCC adopts the 6-kV GCTs (gate-commutated thyristors) that are commercially available in the market, the switching frequency should be less than 200Hz to improve conversion efficiency. Theoretical analysis developed in this paper reveals that the most suitable triangular-carrier frequency is 125Hz or 175Hz. Simulated waveforms obtained from a three-phase 66-kV, 200-MW DSCC are included to verify this analysis. The analytical and simulated results agree well with each other.

Ultra-Low Power, Low Phase Noise 10 GHz LC VCO in the Subthreshold Regime

A new design for an ultra-low power, low phase noise differential 10 GHz LC voltage-controlled oscillator (VCO) which is biased in the subthreshold regime, is presented in the 0.18 μm CMOS process, for the first time. The designed circuit topology is an NMOS only cross-coupled LC-tank VCO which has an extra symmetric centre tapped inductor between the source ends of the cross-coupled transistors. Using this inductor leads to an improvement of the phase noise of VCO about 3.5 dB. At the supply voltage of 0.46 V, the output phase noise is －107.8 dBc/Hz at 1 MHz offset frequency from the carrier frequency of 10.53 GHz, so that the dc power consumption is only 0.346 mW. Tuning range is between 10.53 GHz to 11.35 GHz which is 7.5% and the figure of merit is －193.8 dB, which this result shows that this is the first VCO design in the subthreshold regime at this frequency. This VCO can be used for multi-standard wireless LAN communication protocols 802.11a/b/g easily by a frequency division of 2 or 4 respectively.

Half-bridge converter based on switched-capacitor resonance without using deadtime control for automotive applications

For virtually all converters and inverters, it is necessary to take care of shot-through and deadtime in the half-bridge subcircuits. Floating gate drive designs are also needed. The additional cost to realise these features becomes a concern in low power applications. This study presents a centre-tapped inductor method added to the bridge to satisfy these constraints cost-effectively. The shoot-through current is under controlled. Using push-pull P and N channel metal-oxide silicon field-effect transistors, the floating or level-shift gate drive can be eliminated and the converter becomes simple. The proposed method has been successfully applied to switched capacitor resonant converter. Formulations of the overlapping and resonant equations have also been developed. It is found that the current in the centre-tapped inductor can be transferred to the resonant inductor with the proposed circuitry with no additional loss involved in the design. Moreover, all the current is under zero-current switching. The design has been validated experimentally and high efficiency is realised using the proposed design.

A 90 nm CMOS LC-Tank Divide-by-3 Injection-Locked Frequency Divider With Record Locking Range

This letter proposes a wide-locking range divide-by-3 injection-locked frequency divider fabricated in the 90 nm 1P9M CMOS technology. The divider consists of an nMOS cross-coupled p-core Armstrong LC oscillator and a center-tapped inductor in series with the pMOSFETs. The pMOSFETs are used as a linear and second harmonic mixer. At the supply voltage of 1 V, the free-running frequency is from 7.84 to 8.42 GHz, the current and power consumption of the divider without buffers are 4 mA and 4 mW respectively. At the incident power of 0 dBm, the locking range is 4.28 GHz (19.8%), from the incident frequency 19.52 to 23.8 GHz.

A current-folded up-conversion mixer and VCO with center-tapped inductor in a SiGe-HBT technology for 5-GHz wireless LAN applications

This paper describes a 5.8-GHz up-conversion mixer core based on a current-folded architecture and a 5-GHz differential emitter-coupled voltage-controlled oscillator (VCO) utilizing a center-tapped inductor and a substrate shield. Both circuits are fabricated in a 0.8-/spl mu/m 45-GHz f/sub T/ SiGe heterojunction bipolar transistor (HBT) technology. The supply voltage range is between -2.3 V and -3.3 V to meet the requirements of mobile circuits. Special care has been taken with the inductor model. A distributed modeling approach was used to generate an inductor model from a geometrical description. This type of model also has the advantage that it can simulate RF effects in both time and frequency domain.