Cellular Array Processor Research Articles

3-D imaging systems and high-speed processing for robot control

Bin picking by a robot in real time requires the performance of a series of tasks that are beyond the capabilities of commercially available state-of-the-art robotic systems. In this paper, a laser-ranging sensor for real-time robot control is described. This sensor is incorporated into a robot system that has been applied to the bin-picking or random-parts problem. This system contains new technological components that have been developed recently at the Environmental Research Institute of Michigan (ERIM). These components (the 3-D imaging scanner and a recirculating cellular-array pipeline processor) make generalized real-time robot vision a practical and viable technology. This paper describes these components and their implementation in a typical real-time robot vision system application.

Image algebra techniques for parallel image processing

An image algebra has been defined which is capable of expressing a wide variety of gray-level image-to-image transformations. The purpose of this paper is fourfold: (1) to introduce the reader to the basic concepts of the image algebra; (2) to show how it suggests a general-purpose cellular pyramid array processor for real time image processing tasks; (3) to demonstrate how the image algebra can be used to formulate the problem of mapping algorithms to specific hardware; and (4) to show how algebraic techniques can be used to develop systematic methods for deriving parallel algorithms.

Comparison of 2-D gel electrophoresis images

This paper reports the design and implementation of an algorithm for pairing protein spots seen on separate 2-D electrophoresis gels. The algorithm consists of a global linear transformation applied to one set of protein spots followed by local matching based on the chamfering technique. The algorithm has been implemented on the CLIP4 family of 2-D cellular array processors.

The dynamically reconfigurable CAP Array Chip I

Array Chip I is a bit-slice processor chip using novel fault-tolerant, large-area integration techniques. It provides 20 1-bit bit-slice processors, or cells, which are controlled from a single microinstruction stream. The chip is implemented in 3-/spl mu/m double-metal n-well CMOS, has 115000 transistors, and an unusually large die size of 500/spl times/650 mil. Prototype yields, with at least 16 cells operational exceed 25%. The chip configuration is controlled by software at run time to form bit-parallel or bit-serial words of arbitrary size and to exclude defective elements. Following system initialization, defective elements are invisible at both the programming and the physical chip interconnect levels. Thirty-six of these chips have been used in a prototype cellular-array parallel processor employing the single-instruction stream, multiple-data stream (SIMD) architecture.

Systolic Optical Cellular Array Processors

Using space-variant pattern recognition of up to 256 3 x 3 patterns of l's and 0's in parallel and inserting image information sequentially in a well-defined pattern, we can construct an optical systolic cellular array processor for 3 x 3 neighborhoods that produces output points at one-third the rate at which points are input. This allows reprogrammable preprocessing of data input.

Fast image generation of construcitve solid geometry using a cellular array processor

A general purpose Cellular Array Processor(CAP) with distributed frame buffers for fast parallel subimage generation has been developed. CAP consists of many processor elements called cells. A cell has video memory for subimage storage, a window controller to map each subimage to an area on the monitor screen, and communication devices, in addition to ordinary microcomputer components such as MPU, RAM, and ROM. Image data in a cell is directly displayed via the video bus. The mapping pattern and the position on the screen of subimages can be changed dynamically. Various hidden surface algorithms can be implemented in CAP using mapping patterns appropriate for the algorithm.Our goal is an efficient interactive visual solid modeler. We adopted a general CSG hidden surface algorithm that enables display of both Boundary representation and Constructive Solid Geometry. A technique for hidden surface removal of general CSG models, requiring less memory space for large models in many cases, has been proposed. This technique subdivides the model into submodels by dividing the CSG tree at union nodes. Imagse of each submodel are generated by a CSG or a z-buffer algorithm. If a submodel is just a primitive, it is processed by the z-buffer algorithm, otherwise by the CSG algorithm. Hidden surface removal between submodels is done by comparing the z values for each pixel which are saved in the z-buffer.

Implementation of a Prototype Cellular Logic Array Processor

A prototype cellular logic array processor (CLAP-4), which has been indigenously constructed using TTL integrated circuits, can process 8 by 4 arrays of 4-bit image data in parallel, i.e. simultaneously, as a consequence of the parallel architecture which enables acceptance of contextual information from the neighbourhood of a pixel. Further CLAP-4 provides 48 arithmetic/logical operations on (up to) three operand images. In this paper, a description of the structure of CLAP-4 is presented.

Two pyramid machine algorithms for edge detection in noisy binary images

This paper presents a pair of fast algorithms which detect edges in noisy binary images. The algorithms run on a parallel hierarchical cellular array processor called a pyramid machine. Example results are illustrated and the time required by each algorithm is discussed.

A flow-mode, self-steering, cellular multiplier-summation processor

Flow-mode or stream-processing digital systems have been proposed in which code, control and data are constantly moving so that multiple instructions are processed concurrently. We show the design of a flow-mode cellular array processor which can perform a number of two's complement fixed-point arithmetic operations. These operations are: three operand addition and/or subtraction, two operand multiplication and vector inner-product. Operand sizes are: 2N bit for addition and subtraction operands, andN bit for multiplication operands. Results are 2N bit. The network can simultaneously operate on 4N+2 datasets with any mix of the above operations being handled. The processor is based on the use of asynchronous cellular arrays. Given a continued flow of input datasets, the effective computation time is worst-case propagation time within one cell. A typical cell contains a 1-bit position 3-input full adder with associated input data storage. Thus the effective computation time is independent of the operand bit length.