Cellular Automata Architecture Research Articles

A non-qubit quantum adder as one-dimensional cellular automaton

A complete quantum addition machine is presented and compared with methods employing unitary transformations first. A quantum half-adder circuit shown earlier can be implemented into each cell of a 1D cellular automaton. An electric Aharonov–Bohm effect version of the quantum circuit is used to illustrate this implementation. Whatever a quantum Turing machine can achieve is realized in the cellular automata architecture we propose here. The coherence requirement is limited to one cell area. The magnetic flux needed is 0.1Φ0, corresponding to 0.414mT for a ring area of 1 square micron or an electric potential of 0.414mV at 1ps with an energy dissipation of 0.041eV per iteration.

QUANTUM COMPUTATION BASED ON ELECTRON SPIN QUBITS WITHOUT SPIN-SPIN INTERACTION

Using electron spin states in a unit cell of three semiconductor quantum dots as qubit states, a scalable quantum computation scheme is advocated without invoking qubit-qubit interactions. Single electron tunneling technology and coherent quantum-dot cellular automata architecture are used to generate an ancillary charge entangled state which is then converted into spin entangled state. Without using charge measurement and ancillary qubits, we demonstrate universal quantum computation based on free electron spin and coherent quantum-dot cellular automata.

Design of new AB2 multiplier over GF(2m) using cellular automata

AB/sup 2/ multiplication over GF(2/sup m/) is an essential operation in modular exponentiation, which is the basic computation for most public key cryptosystems. The authors present a new architecture that can perform AB/sup 2/ multiplication over GF(2/sup m/) in m clock cycles using cellular automata. The proposed cellular automata architecture is also well suited to VLSI implementation because it is simple, regular, modular, and cascadable.

Toward micro-scale spatial modeling of gentrification

A simple preliminary model of gentrification is presented. The model is based on an irregular cellular automaton architecture drawing on the concept of proximal space, which is well suited to the spatial externalities present in housing markets at the local scale. The rent gap hypothesis on which the model's cell transition rules are based is discussed. The model's transition rules are described in detail. Practical difficulties in configuring and initializing the model are described and its typical behavior reported. Prospects for further development of the model are discussed. The current model structure, while inadequate, is well suited to further elaboration and the incorporation of other interesting and relevant effects.

Real-time morphology processing using highly parallel 2-D cellular automata CAM/sup 2/

Mathematical morphology is a promising computer paradigm based on set theory and has many applications in image processing. Although some architectures have been proposed, there are as yet no compact, practical computers that can handle a variety of morphological operations with large, complex structuring elements at video rates. This has prevented the great potential of morphology from being fully realized. This paper describes a morphology processing method that uses a highly parallel two-dimensional (2-D) cellular automaton architecture called it CAM2 (Cellular AutoMata on Content Addressable Memory). New mapping methods achieve high-throughput complex morphology processing. Evaluation results show that CAM2 performs one morphological operation for basic structuring elements within 30 micros. Furthermore, CAM2 can also handle an extremely large and complex structuring element of 100x100 at video rates. CAM2 will increase the potential use of morphology and make a significant contribution to the development of various real-time image processing systems.

CAM/sup 2/: a highly-parallel two-dimensional cellular automaton architecture

Cellular automaton (CA) is a promising computer paradigm that can break through the von Neumann bottleneck. Two-dimensional CA is especially suitable for application to pixel-level image processing. Although various architectures have been proposed for processing two-dimensional CA, there are no compact, practical computers. So, in spite of its great potential, CA is not widely used: This paper proposes a highly-parallel two-dimensional cellular automaton architecture called CAM/sup 2/ and presents some evaluation results. CAM/sup 2/ can attain pixel-order parallelism on a single board because it is composed of a CAM, which makes it possible to embed an enormous number processing elements (PEs), corresponding to CA cells, onto one VLSI chip. Multiple-zigzag mapping and dedicated CAM functions enable high-performance CA processing. The performance evaluation results show that 256 k CA cells, which correspond to a 512/spl times/512 picture, can be processed by a CAM/sup 2/ on a single board using deep submicron process technology. The processing speed is more than 10 billion CA cell updates per second. This means that more than a thousand CA-based image processing operations can be done on a 512/spl times/512 pixel image at video rates (33 msec). CAM/sup 2/ will widen the potentiality of CA and make a significant contribution to the development of compact and high-performance systems.

Geometrical Shape Recognition Using a Cellular Automaton Architecture and its VLSI Implementation

This paper presents a new, fast geometrical shape recognition technique based on the properties of cellular automata (CA). The VLSI implementation of the architecture developed for this purpose is also presented. The digitized binary image of the geometrical shape is loaded onto a 2D CA grid. This binary image is the initial global state of the CA. The CA evolves in time until a final stable global state is reached. The geometrical shapes are classified into four different categories, according to the symmetries of their final stable global state, and are then recognized. Eleven geometrical shapes have been recognised using the proposed technique. The die size dimensions of the chip for a 8 × 8 pixel image are 2.56 mm × 2.70 mm = 6.91 mm2, and itsmaximumfrequency of operation is 35 MHz. Targeted applications include classification and inspection tasks in industry.

Collision-free path planning for a diamond-shaped robot using two-dimensional cellular automata

This paper presents a new parallel algorithm for collision-free path planning of a diamond-shaped robot among arbitrarily shaped obstacles, which are represented as a discrete image, and its implementation in VLSI. The proposed algorithm is based on a retraction of free space onto the Voronoi diagram, which is constructed through the time evolution of cellular automata, after an initial phase during which the boundaries of obstacles are identified and coded with respect to their orientation. The proposed algorithm is both space and time efficient, since it does not require the modeling of objects or distance and intersection calculations. Additionally, the proposed twodimensional multistate cellular automaton architecture achieves high frequency of operation and it is particularly suited for VLSI implementation due to its inherent parallelism, structural locality, regularity, and modularity.

An efficient algorithm for the largest empty figure problem based on a 2D cellular automaton architecture

An efficient algorithm for determination of the largest empty figure that can be placed between a set of sites on a plane and its VLSI implementation are presented in this paper. The proposed algorithm is based on the Voronoi diagram in the ϱ1 metric which is established through the time evolution of 2-Dimensional Cellular Automata. The proposed algorithm is fast and efficient, and the 2-Dimensional Cellular Automaton architecture presented in this paper achieves a high frequency of operation. A Von-Neumann neighbourhood processor was implemented on a single VLSI chip using a 1.2 μm Double Layer Metal CMOS technology.

A new hardware module for automated visual inspection based on a cellular automaton architecture

This paper presents the design and VLSI implementation of a new automated visual inspection system based on a cellular automaton architecture, suitable for circular object inspection. Cellular Automata (CA) transform the area of the object of interest into a number of evolution steps in the CA space. The proposed technique does not require the extraction of image features, such as boundary length and total area, which are computationally expensive in other methods. The die size dimensions of the chip, for a 16×16 pixel image, are 3.73 mm×3.09 mm=11.52 mm2 and its maximum frequency of operation is 25 MHz. Experimental results using computer-generated images, as well as real images obtained and processed through a commercial vision system, showing the suitability of the proposed hardware module for detecting circular objects, are also presented. Targeted applications include inspection tasks (accept/reject operations) of circular objects, such as tablets in the pharmaceutical industry, and detection of uncoated areas, foreign objects and level of bake in the confectionery and food industry.

A cellular automaton for the determination of the mean velocity of moving objects and its VLSI implementation

A new algorithm for the determination of the mean velocity of a moving object, using the properties of Cellular Automata, is presented in this paper. The mean velocity is calculated along the centra axis perpendicular to the lens of the vision system. The motion of the object is restricted to translation (angular velocity is zero) and to one moving object in the scene. Experimental results for the determination of the mean velocity and its computational error are also presented. The algorithm presented in this paper does not require the calculation or the extraction of image features, such as area and shape, line segments, characteristic points, corners, etc. The design and VLSI implementation of a Cellular Automaton architecture is also presented for the efficient realisation of the algorithm.

A hybrid cellular automaton/neural network classifier for multi-valued patterns and its VLSI implementation

A multi-valued pattern classifier with high discrimination sensitivity and its VLSI implementation proposal on a single chip are presented in this paper. The classification scheme is based on the combination of a reconfigurable Cellular Automaton and a Neural Network architecture. A 2-D Reconfigurable Hybrid Additive Cellular Automaton (RHACA) architecture amplifies the Hamming distance between patterns, whereas a neural network architecture, implemented in digital form, assigns vectors of weighing coefficients which take into account the relative significance of the sites on the 2-D lattice. The proposed classifier is able to operate successfully even for pattern classes of small difference, or for patterns that lie on the decision boundaries between classes. If the training and processing phases are not partitioned, the proposed classification scheme is able to operate in partially exposed environments. With the proper setting of admittance levels into the classes of multi-valued patterns involved, the proposed classifier can also operate on patterns with partly missing data. The proposed multi-valued pattern classifier can be realized on a single VLSI chip with dimensions 7.73 mm × 8.14 mm = 62.96 mm 2 and the expected frequency of operation for the chip is 50 MHz.

A Parallel Skeletonization Algorithm Based on Two-Dimensional Cellular Automata and its VLSI Implementation

This paper presents a new parallel algorithm for binary object skeletonization and its implementation in VLSI. The proposed skeletonization algorithm is based on a digital geometry concept known as the 'Voronoi diagram, which is established, after an edge detection pre-processing step, through the time evolution of Cellular Automata. The proposed algorithm is both space and time efficient, since it does not require any distance calculations and ordering of distances as in the case of other skeletonization algorithms nor the application of complex 'template' criteria to guarantee object connectiveness as in the case of thinning algorithms. Additionally, the proposed Cellular Automaton architecture achieves high frequency of operation and it is especially suited for VLSI implementation due to its inherent parallelism, structural locality, regularity and modularity. A set of quantitative measures was defined in this paper in order to evaluate the performance of the proposed algorithm. It was found that the proposed algorithm for pattern skeletonization outperforms already existing algorithms, with respect to these measures.

A new, cellular automaton-based, nearest neighbor pattern classifier and its VLSI implementation

A new, parallel, nearest-neighbor (NN) pattern classifier, based on a 2D Cellular Automaton (CA) architecture, is presented in this paper. The proposed classifier is both time and space efficient, when compared with already existing NN classifiers, since it does not require complex distance calculations and ordering of distances, and storage requirements are kept minimal since each cell stores information only about its nearest neighborhood. The proposed classifier produces piece-wise linear discriminant curves between clusters of points of complex shape (nonlinearly separable) using the computational geometry concept known as the Voronoi diagram, which is established through CA evolution. These curves are established during an "off-line" operation and, thus, the subsequent classification of unknown patterns is achieved very fast. The VLSI design and implementation of a nearest neighborhood processor of the proposed 2D CA architecture is also presented in this paper.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Bistable saturation due to single electron charging in rings of tunnel junctions

The behavior of rings of four small-capacitance tunnel junctions that are charged with two extra electrons is examined. Single electron charging effects result in quantization of charge on the metal electrode islands. To minimize the total electrostatic energy, the electrons localize on opposite electrodes, leading to a charge alignment in one of two configurations. We consider such rings as cells that may be capacitively coupled to each other in a cellular automaton architecture. The interaction between cells results in strong bistable saturation in the cell’s charge alignment which may be used to encode binary information. Lines of such cells can be viewed as binary wires.

2-Dimensional minimum cost path planning using a cellular automaton architecture

A new algorithm for the estimation of the minimum cost path between a pair of points on a binary map and it's VLSI implementation, using a new, multi-state, 2-D Cellular Automata (CA) architecture, are presented in this paper. The main advantages of the proposed architecture, when compared to already existing ones, are that storage requirements are reduced to a minimum and the speed of operation is very high, since no internal memory transfer operations are required. A 4 × 4 module was designed to serve as the basic building block for the implementation of larger dimension architectures. The die size for this module is 5.81 mm × 5.45 mm = 31.69 mm 2 and the speed of operation is 45 MHz.