CDMOS Process Research Articles

Design, Fabrication and Measurement of LDNMOSSCR Devices with Appropriate ESD Protection Window for 18V HV CDMOS Process

LDMOS embedded SCR is a normal way to improve the ESD robustness for smart power technologies, but it doesn’t always have the proper ESD window for a given application. In this paper, LDNMOS-SCR of four variants structures have been inves-tigated based on a high-voltage (HV) 0.5μm 18V HV CDMOS process with 2D device simulation and silicon verification. TLP testing results demonstrated that those devices successfully elevate the second breakdown current I t2 from original 1.146A to above 3A; source isolated device has a lower V t1 (45.79V) than source non-isolated devices; the V h of the four devices is related to their structure, and their I h are all above 800mA, which is big enough to ensure the latch-up immunity under ESD stresses in HV applications. The device with its source isolated from PSUB is the suitable ESD protection device for HV 18V CDMOS technology owning to its strong ESD robustness, low V t1 , small R on and sufficiently big I h .

New embedded DDSCR structure with high holding voltage and high robustness for 12-V applications**Project supported by the National Natural Science Foundation of China (Grant Nos. 61704145, 61774129, and 61827812), the Natural Science Foundation of Hunan Province, China (Grant No. 2019JJ50609), and the Key Technology Program of Changsha City, China (Grant No. kq1902042).

A new dual directional silicon-controlled rectifier based electrostatic discharge (ESD) protection device suitable for 12-V applications is proposed in this paper. The proposed device (NPEMDDSCR) is based on the embedded DDSCR (EMDDSCR) structure, in which the P+ electrode and P+ injection are removed from the inner finger. Compared with the conventional modified DDSCR (MDDSCR), its high holding voltage meets the requirements for applications. Compared with the embedded DDSCR (EMDDSCR), it has good conduction uniformity. The MDDSCR, EMDDSCR, and NPEMDDSCR are fabricated with an identical width in a 0.5-μm CDMOS process. In order to verify and predict the characteristics of the proposed ESD protection device, a transmission line pulse (TLP) testing system and a two-dimensional device simulation platform are used in this work. The measurements demonstrate that the NPEMDDSCR provides improved reliability and higher area efficiency for 12 V or similar applications. The measurement results also show that the NPEMDDSCR provides higher robustness and better latch-up immunity capability.

A compact LDMOS DDSCR for HV ESD protections with high robustness and reliability

The LDMOS-based silicon controlled rectifier (SCR) is commonly used in high voltage (HV) electrostatic discharge (ESD) protection due to its great current handling capability per area and HV protection ability. In this paper, an improved LDMOS-based dual direction SCR (LDMOS-DDSCR) device is designed by replacing floating N+ region with electrically-connected P+, N+ and P+ regions to enhance its ESD robustness, which is verified in a 0.5-μm (1p2m) 18 V HV CDMOS process. The internal mechanism of the proposed device is analyzed using two-dimension (2D) TCAD simulations, and the ESD performance is characterized by means of transmission line pulse (TLP) and very-fast TLP (VFTLP) measurements. Compared with the conventional LDMOS-DDSCR, the failure current of the compact LDMOS-DDSCR raises from 2.00 A to 4.02 A (increased by 101%), and the trigger voltage reduces from 44.28 V to 39.76 V, without sacrificing layout area. Furthermore, the TLP I-V curves of the proposed LDMOS-DDSCR are measured at different temperatures ranging from 25 °C to 125 °C, which proves its reliability and show potential use in the applications of high voltage integrated circuits.

A Novel High Holding Voltage Dual-Direction SCR With Embedded Structure for HV ESD Protection

In order to boost the holding voltage of the multi-fingered dual-direction silicon-controlled rectifier, a novel embedded topology is proposed instead of the traditional interdigital multi-finger arrangement. It is verified in a 0.5- $\mu \text{m}$ 18-V standard CDMOS process and applied to the high-voltage electro-static discharge (ESD) protection. With equivalent circuit and 2D device simulation, the operation principle and working mechanism are analyzed. According to the TLP-test results, the holding voltage of the multi-finger device is greatly improved from 7.62 V (traditional interdigital structure) to 19.67 V (the proposed embedded structure), and it has a narrower ESD design window (9.26 V) than that of the interdigital counterpart (15.17 V). Furthermore, the principle of the multi-finger device with embedded topology features a superior holding voltage is explained by using the model of ladder resistance network. It is concluded that the Ron of the embedded structure is determined by the size of topology and almost unaffected by the number of fingers.

Design and analysis of different trigger techniques for ESD clamp circuit in 0.5-µm 5 V/18 V CDMOS process

In this work, gate-driven, substrate-triggered and gate-substrate-triggered techniques for both 5V NMOS-based and 18V NLDMOS-based power clamps under electrostatic discharge (ESD) stress were investigated in details. Schematics of the three trigger designs were depicted and their physical mechanisms were studied at first. To verify and make comparisons of their performance, they were fabricated in a standard 0.5-μm 5V/18V CDMOS process and characterized by transmission line pulse (TLP) test system, respectively. Experimental results show that 5V NMOS-based power clamp with substrate-triggered technique has the lowest trigger voltage (∼8.37V) and the highest failure current (∼3.58A), and 18V gate-substrate-triggered design based on NLDMOS has low trigger voltage (∼34.02V) and greatest robustness (It2=3.32A). Therefore, as for low-voltage NMOS-based ESD power clamps, substrate-triggered design obtains the most superior ESD protection performance; but for high-voltage power clamps, gate-substrate-triggered technique can make NLDMOS actualize uniform current conduction and better ESD robustness.

Cathode Side Engineering to Raise Holding Voltage of SCR in a 0.5-㎛ 24 V CDMOS Process

A set of novel silicon controlled rectifier (SCR) devices’ characteristics have been analyzed and verified under the electrostatic discharge (ESD) stress. A ring-shaped diffusion was added to their anode or cathode in order to improve the holding voltage (Vh) of SCR structure by creating new current discharging path and decreasing the emitter injection efficiency (γ) of parasitic Bipolar Junction Transistor (BJT). ESD current density distribution imitated by 2- dimensional (2D) TCAD simulation demonstrated that an additional current path exists in the proposed SCR. All the related devices were investigated and characterized based on transmission line pulse (TLP) test system in a standard 0.5-μm 24 V CDMOS process. The proposed SCR devices with ring-shaped anode (RASCR) and ring-shaped cathode (RCSCR) own higher Vh than that of Simple SCR (S_SCR). Especially, the Vh of RCSCR has been raised above 33 V. What’s more, their holding current is kept over 800 mA, which makes it possible to design power clamp with SCR structure for on chip ESD protection and keep the protected chip away from latch-up risk.

Robust lateral double‐diffused MOS with interleaved bulk and source for high‐voltage electrostatic discharge protection

A device with bulk and source interleaved dotting is fabricated in a 0.5-µm 24 V CDMOS process, and the root cause of why it improves the multi-finger high-voltage lateral double-diffused MOS (LDMOS)’s electrostatic discharge (ESD) robustness is detected by Atlas three-dimensional device simulation and transmission line pulse system. Such device structure obtains strong ESD robustness by enlarging the intrinsic base resistance without increasing device area and sacrificing any ESD performance of nLDMOS. The measurement results demonstrated that, compared with traditional gate-grounded nLDMOS (GG-nLDMOS) with a total length of 400 μm, the proposed device can effectively raise the secondary breakdown current (I t2) from 2.43 A up to 5.55 A, and enhance the ESD current discharge efficiency from 0.29 to 0.70 mA/μm2.

Novel LDNMOS embedded SCR with strong ESD robustness based on 0.5 μm 18 V CDMOS technology

A novel LDNMOS embedded silicon controlled rectifier (SCR) was proposed to enhance ESD robustness of high-voltage (HV) LDNMOS based on a 0.5 μm 18 V CDMOS process. A two-dimensional (2D) device simulation and a transmission line pulse (TLP) testing were used to analyze the working mechanism and ESD performance of the novel device. Compared with the traditional GG-LDNMOS, the secondary breakdown current (It2) of the proposed device can successfully increase from 1.146 A to 3.169 A with a total width of 50 μm, and ESD current discharge efficiency is improved from 0.459 mA/μm2 to 1.884 mA/μm2. Moreover, due to their different turn-on resistances (Ron), the device with smaller channel length (L) owns a stronger ESD robustness per unit area.

Design and analyze of transient-induced latch-up in RS485 transceiver with on-chip TVS

The occurrence of transient induced latch up (TLU) in RS485 transceiver IC with on-chip Transient Voltage Suppressor (TVS) under electrical fast transient (EFT) test is studied. A RS485 transceiver fabricated by a 0.5-μm CDMOS process was used in the test, the latch-up and emission microscope (EMMI) tests are used for confirming the reason and position of latch-up. The trigger current injecting into the transceiver through RO port and generating the substrate current is the major cause of TLU under EFT test. Some measures in layout are taken to improve the TLU immunity of RS485 transceiver against EFT test.

Robust dual-direction SCR with low trigger voltage, tunable holding voltage for high-voltage ESD protection

An LDNMOS-based and an LDPMOS-based dual direction silicon controlled rectifier (DDSCR) devices have been designed and fabricated in a 0.5-μm 5V/18V high voltage (HV) CDMOS process. These devices can be used to protect pins with a voltage range that goes above and below the ground by discharging electrostatic current in both positive and negative directions. A 2-dimension (2D) device simulation and a transmission line pulse (TLP) measurement were used to predict and characterize the ESD performance of the two DDSCR devices. Compared to LDNMOS-based DDSCR, LDPMOS-based DDSCR is excellent for its relatively low trigger voltage of 33V and strong electrostatic discharge (ESD) current handling capability of 87mA/μm. Furthermore, the holding voltage of LDPMOS-based DDSCR can be elevated by tuning layout parameter. Such a device has been applied to I/O bus terminals of a data interface circuit for its on-chip ESD protection.

Design, fabrication and test of novel LDMOS-SCR for improving holding voltage

A novel structure, which is achieved by inserting P+ slots into the polygate of traditional LDMOS-SCR, has been designed to improve the holding voltage. The proposed structure called GateDot was fabricated in 0.5μm 18V CDMOS process. In this study, comparative analysis is carried out to make detailed comparisons between conventional LDMOS-SCR and the new proposed structure. GateDot not only maintains superiorities of low trigger voltage and strong capability of shunting ESD current in conventional LDMOS-SCR structure, but also increases the holding voltage greatly. To verify its advantages, theoretical analysis and TCAD device simulations were provided during the course of research. TLP (Transmission Line Pulse) test has been done and the results show that the holding voltage can effectively increase from 7.00V to 10.17V, 45.29% increment compared to traditional LDMOS-SCR, which is highly appeal to the simulation results.

A feedback loop regulated bootstrap driver circuit with improved drive capability for high voltage buck DC–DC converter

A novel bootstrap driver circuit applied to high voltage buck DC–DC converter is proposed. The gate driver voltage of the high side switch is regulated by a feedback loop to obtain accurate and stable bootstrapped voltage. The charging current of bootstrap capacitor is provided by the input power of the DC–DC converter directly instead of internal low voltage power source, so larger driver capability of the proposed circuit can be achieved. The bootstrap driver circuit starts to charge the bootstrap capacitor before the switch node SW drop to zero voltage at high-side switch off-time. Thus inadequate bootstrap voltage is avoided. The proposed circuit has been implemented in a high voltage buck DC–DC converter with 0.6µm 40V CDMOS process. The experimental results show that the bootstrap driver circuit provides 5V stable bootstrap voltage with higher drive capability to drive high side switch. The proposed circuit is suitable for high voltage, large current buck DC–DC converter.

An Improved Hiccup Mode Short-Circuit Protection Technique With Effective Overshoot Suppression for DC–DC Converters

Based on the analysis of the overshoot during the process of short-circuit recovery, an improved hiccup mode protection technique with effective overshoot suppression is presented in this paper. The hiccup mode is activated by the error amplifier (EA) output rather than the feedback voltage. And when the voltage exceeds the high-clamping voltage, the soft-start voltage will be quickly discharged to zero and a new soft-start cycle will attempt to restart the converter. The proposed control method makes the EA output voltage rapidly decline once short-circuit recovery happens, which is very effective for the suppression of overshoot. In addition, the circuit has combined with a foldback current limiting method to further improve the effect of short-circuit protection and overshoot suppression. The proposed technique has been successfully applied to a peak current mode buck converter with Nuvoton 0.6-μm 5 V/18 V Low-V <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$_{\rm gs}$</tex></formula> CDMOS process. The experimental results show that even in extreme cases, this method can effectively suppress the overshoot and the overshoot is almost zero.

Design of a switching frequency adaptive slope compensation circuit for frequency synchronous DC–DC converters

The inductor value of the frequency synchronous DC–DC converter is related to the operating switching frequency. In order to optimize the performance of stability, transient response and load capability, this paper presents a switching frequency adaptive slope compensation circuit. The circuit adjusts the slope compensation by automatic operation according to the synchronized switching frequency to avoid excessive compensation. The proposed circuit has been implemented in a high voltage buck DC–DC converter with 0.6μm CDMOS process. The test results indicate that fast transient response and load capability are realized and the stability is achieved without sub-harmonic oscillation in the whole synchronous frequency range. Graphical abstract [Display omitted] Highlights► A frequency adaptive slope compensation circuit is proposed. ► The slope compensation adjusts with the synchronized switching frequency. ► Avoids excessive compensation and sub-harmonic oscillation. ► The circuit is implemented and verified in a frequency synchronous DC–DC converter.► Transient response and load capability have well performance in the frequency range.

Investigation of pickup effect for multi-fingered ESD devices in 0.5 µm 5V/18V CDMOS process

Pickup effect for 5V NMOS and 18V lateral double-diffused NMOS under electrostatic discharge (ESD) stress is investigated and characterised by a transmission line pulse test system in a standard 0.5 µm 5V/18V CDMOS process, respectively. Experimental results show that 5V low-voltage multi-fingered NMOS devices cannot be turned-on uniformly with more added inner pickups and thus the ESD robustness degrades. For 18V high-voltage multi-fingered LDNMOS structures, it is critical to merge all pickups with the P-well guard-ring of the device to achieve uniform current conduction and better ESD performance.

A Time-Programmable Soft-Start Circuit with Hiccup Control

A time-programmable soft-start circuit with hiccup control for switching regulators is presented. By using a novel soft-start voltage generating circuit, the soft-start time can be set internally and externally by one pin which enhances the flexibility for applications. A hiccup control has also been integrated into the circuit to deal with the problems of current inrush and voltage overshot in short circuit case which can effectively improves the system reliability. The proposed soft-start circuit has been fabricated with UMC 0.35μm CDMOS process successfully, and the detailed experimental results are shown at the end of the article.

Design of high efficiency dual-mode buck DC-DC converter

A buck DC—DC switching regulator with high efficiency is implemented by automatically altering the modulation mode according to load current, and it can operate with an input range of 4.5 to 30 V. At light load current, the converter operates in skip mode. The converter enters PWM mode operation with increasing load current. It reduces the switching loss at light load and standby state, which results in prolonging battery lifetime and stand-by time. Meanwhile, externally adjustable soft-start minimizes the inrush supply current and avoids the overshoot of output voltage at initial startup. The regulator is fabricated by a 0.6 μm CDMOS process. The test results show that, under the condition of 3.3 V output, the efficiency is up to 64% at 5 mA and the maximum efficiency is 95.5%.

Realizing High-Voltage Junction Isolated LDMOS Transistors With Variation in Lateral Doping

High-voltage lateral diffused metal-oxide semiconductor (LDMOS) transistors with a variation in the lateral doping (VLD) of drift regions are demonstrated in junction isolation technology using a fully implanted CDMOS process. The VLD profile is realized by using an analytical approach reported previously. The analytical model is verified through simulations and experiment. Results indicate that higher breakdown voltages can be achieved for a given drift length using a VLD profile in comparison to uniform doping while offering a good tradeoff between breakdown voltage and specific on-resistance.

A fast switching segmented anode NPN controlled LIGBT

An ultrafast low energy loss lateral insulated gate bipolar transistor (LIGBT) with a novel segmented anode structure is demonstrated. The anode comprises segments of p/sup +/ and n/sup +//p (n/sup +/ region formed within a p-type region) along the width of the device. By simply varying the ratio of these segments the tradeoff between conduction and switching losses can be varied. Unlike an anode shorted structure this does not exhibit an undesirable snapback in its on-state characteristics. This structure is simple to realize in a CDMOS process without the need for any additional process steps.