Cascode Power Amplifier Research Articles

Design of K-Band CMOS Extended Cascode Power Amplifier With Second Harmonic Termination to Enhance Output Power

Design of K-Band CMOS Extended Cascode Power Amplifier With Second Harmonic Termination to Enhance Output Power

A Balanced Distributed Cascode Power Amplifier With an Integrated Chebyshev Load Balancer for Full-Duplex Wireless Operation

A Balanced Distributed Cascode Power Amplifier With an Integrated Chebyshev Load Balancer for Full-Duplex Wireless Operation

A 5.8 GHz 1.8 V +20 dBm 32.5% PAE Power Amplifier for a Short-Range Over-the-Air WPT Application.

This paper presents a 5.8 GHz differential cascode power amplifier for an over-the-air wireless power transfer application. Over-the-air wireless power transfer provides a variety of benefits in several applications such as the Internet of Things and medical implantation applications. The proposed PA features two fully differentially active stages with a custom-designed transformer to provide a single-ended output. The custom-made transformer shows a high quality factor, as high as 11.6 and 11.2 for the primary and secondary sides at 5.8 GHz. Fabricated using a standard 180 nm CMOS process, the amplifier achieves input and output matching of -14.7 dB and -29.7 dB, respectively. To achieve a high power level and efficiency, accurate optimization through power matching, Power Added Efficiency (PAE), and the design of the transformer are carried out while the supply voltage is limited to 1.8 V. Measurement results show a 20 dBm output power with a PAE as high as 32.5%, which makes the PA suitable for application, and it can be implanted while arrayed with various antenna arrays. Finally, a FOM is introduced to compare the performance of the work with similar works in the literature.

A Broadband SiGe HBT Cascode Power Amplifier Achieving Watt-Level Peak Output Power With 38.6% PAE and 90.9% Large-Signal Fractional Bandwidth

This brief presents a broadband SiGe power amplifier that achieves 30.1 dBm peak <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{P}_{SAT}$ </tex-math></inline-formula> , 38.6% peak power-added efficiency (PAE), 90.9% large-signal fractional bandwidth (FBW) and a 3 dB bandwidth from 5.4 to 13.8 GHz. A balanced topology with two-stage, four-way combing is utilized to achieve watt-level output power and high-power efficiency in a wide range of operating frequency. Power stage is optimized and simulated from the perspective of high output power. At the output stage, a 90° coupler and two transformers are co-optimized for broadband output power combining as well as power matching. This balanced PA is implemented in a 0.13- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\boldsymbol {\mu }\text{m}$ </tex-math></inline-formula> SiGe BiCMOS process with a chip area (with pads) of 2.31 mm2.

A Dual-Band 47-dB Dynamic Range 0.5-dB/Step DPA with Dual-Path Power-Combining Structure for NB-IoT.

This paper presents a digital power amplifier (DPA) with a 43-dB dynamic range and 0.5-dB/step gain steps for a narrow-band Internet of Things (NBIoT) transceiver application. The proposed DPA is implemented in a dual-band architecture for both the low band and high band of the frequency coverage in an NBIoT application. The proposed DPA is implemented in two individual paths, power amplification, and power attenuation, to provide a wide range when both paths are implemented. To perform the fine control over the gain steps, ten fully differential cascode power amplifier cores, in parallel with a binary sizing, are used to amplify power and enable signals and provide fine gain steps. For the attenuation path, ten steps of attenuated signal level are provided which are controlled with ten power cores, similar to the power amplification path in parallel but with a fixed, small size for the cores. The proposed implementation is finalized with output custom-made baluns at the output. The technique of using parallel controlled cores provides a fine power adjustability by using a small area on the die where the NBIoT is fabricated in a 65-nm CMOS technology. Experimental results show a dynamic range of 47 dB with 0.5-dB fine steps are also available.

H-Band Broadband Balanced Power Amplifier in 250-nm InP HBT Technology Using Impedance-Transforming Balun

A broadband power amplifier in a 250-nm InP HBT technology is presented, working at full <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">H</i> -band (220–320 GHz). A cascode transistor is employed as a power cell to achieve high gain and power at <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">H</i> -band. Two-stage cascode power amplifier is designed with input and output impedance of not 50 but 25 Ω, reducing the impedance transformation ratio and allowing the broadband matching networks. Two power-amplifier channels are power-combined using on-chip baluns which performs the impedance transformation from 25 to 50 Ω. The balun operation is based on the electromagnetic field conversion between coplanar waveguide and microstrip line. It does not rely on long transmission lines with frequency-dependent length, so that it occupies a very compact area and exhibits a broadband performance. It also enables power amplifiers to operate in the balanced mode, allowing the area reduction and stable operation. Substrate modes and in-band resonances in InP substrate, which seriously degrade circuit performance and limits bandwidth, are effectively suppressed by the reduced on-chip ground and balanced operation. The fabricated power amplifier shows a measured small-signal gain of 20.8 dB at 232 GHz with a 3-dB bandwidth larger than 51 GHz (20.8%). Output power also exhibits a broadband performance of 8.0±1.5 dBm from 220 to 295 GHz with power gain larger than 10.5 dB, corresponding to a large-signal 3-dB bandwidth larger than 75 GHz. This belongs to an excellent bandwidth in both small- and large-signal performance among the reported <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">H</i> -band power amplifiers.

A 28-GHz CMOS Power Amplifier Linearized by Dynamic Conductance Control and Body Carrier Injection

A 28-GHz linear CMOS cascode power amplifier (PA) that adopts two types of analog linearization methods, dynamic conductance control (DCC) and body carrier injection (BCI), is presented here. The former method controls the load conductance of a common-source (CS) amplifier according to the input power of the PA. This improves the AM-AM and AM-PM characteristics of the cascode PA, which is also analyzed with an equivalent circuit model. The latter injects the carrier signal into the body of a common-gate (CG) transistor, which increases the voltage headroom of the CS transistor. This improves the AM-AM of the cascode PA and also helps to stabilize the PA by reducing the drain-source capacitance of the CG transistor. The proposed PA is fabricated in a 65-nm CMOS process and shows a gain of 15.9 dB, an output 1-dB compression point of 17.7 dBm, and a saturation output power of 19.1 dBm with a peak power-added efficiency (PAE) of 41.2% at 28 GHz.

K-Band Hetero-Stacked Differential Cascode Power Amplifier with High Psat and Efficiency in 65 nm LP CMOS Technology

A K-band complementary metal-oxide-semiconductor (CMOS) differential cascode power amplifier is designed with the thin-oxide field effect transistor (FET) common source (CS) stage and thick-oxide FET common gate (CG) stage. Use of the thick-oxide CG stage affords the high supply voltage to 3.7 V and enables the high output power. Additionally, simple analysis shows that the gain degradation due to the low cut-off frequency of the thick-oxide CG FET can be compensated by the high output resistance of the thick-oxide FET if the inter-stage node is neutralized. The measured results of the proposed power amplifier demonstrate the saturated output power of the 23.3 dBm with the 31.3% peak power added efficiency (PAE) at 24 GHz frequency. The chip is fabricated in 65-nm low power (LP) CMOS technology and the chip size including all pads is 700 μm × 630 μm.

Full D-Band Transmit–Receive Module for Phased Array Systems in 130-nm SiGe BiCMOS

This letter presents a D-band (110 to 170 GHz) transmit- receive module in 0.13-μm silicon-germanium (SiGe) BiCMOS for phased-array applications. The module includes single-pole double throw (SPDT) switches, a low noise amplifier (LNA), a power amplifier (PA), and two variable gain amplifiers (VGAs). A broadband quarter-wave SPDT is designed with power handling capacity of 17 dBm and a state-of-the-art insertion loss of 2 dB at 140 GHz. The three-stage cascode LNA and PA and the two-stage phase-compensated VGA cover the entire D-band. In the receive mode, the module has a measured peak gain of 28.3 dB with a 3-dB bandwidth (BW) of 110-170 GHz, along with a minimum noise figure (NF) of 9 dB (at 120 GHz) and an IP1dB of -21 dBm. In the transmit mode, the peak gain is 22.4 dB within a 3-dB BW of 113-170 GHz, while the OP1dB is 7 dBm and the Psat 9.5 dBm at 140 GHz.

A Broadband Power Amplifier in 130-nm SiGe BiCMOS Technology

This letter describes an ultrabroadband power amplifier (PA) in a 130-nm SiGe:C BiCMOS technology. To achieve this broadband while keeping a compact chip size, an on-chip transformer-based dual-LC-tank power matching method is proposed and implemented for achieving this 54.8% fractional large-signal 3-dB bandwidth (28.5-50 GHz). Additionally, a high quality factor (Q) bypass MOM capacitor is proposed and implemented in the transistor layout to decrease the parasitic inductance influence for increasing the gain and keep unconditional stability of the PA. The complete PA achieves a measured saturated output power of 19.2 dBm with 21.5-GHz (28.5-50 GHz) large-signal -3-dB bandwidth at 3.3-V power supply. This broadband PA is only 0.63 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , and the measured S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">21</sub> is higher than 22.5 dB from 18.5 to 50 GHz with recorded 70.3% fractional small-signal 3-dB bandwidth for silicon-based cascode PA. The measured peak OP1dB is 16.8 dBm at 44 GHz, and the maximum power-added efficiency (PAE) is 23.9% at 32 GHz.

A MM-Wave Current-Mode Inverse Outphasing Transmitter Front-End: A Circuit Duality of Conventional Voltage-Mode Outphasing

This article presents a millimeter-wave (mm-wave) transmitter (TX) front-end employing a new inverse outphasing architecture with current-mode power amplifiers (PAs). This study on the conventional outphasing operation reveals its strong dependence on its voltage-mode driving source assumption and thus exhibits major limitations at mm-wave, since efficient and linear mm-wave PAs often behave as current sources. To address this challenge, we propose a current-mode inverse outphasing architecture that employs current-mode driving sources and is inherently compatible with mm-wave linear PAs. Moreover, the conventional series outphasing combiner is replaced by a much simpler and low-loss parallel power combining scheme. Closed-form mathematical expressions are derived for both the outphasing and inverse outphasing operations, including the active load modulation, Chireix compensations, and outphasing efficiency, which fundamentally explains the limitations of the conventional approach and the advantages of the inverse outphasing architecture. Further theoretical analysis discovers a circuit duality relationship between outphasing and inverse outphasing architectures, which offers unique circuit intuitions. As a proof-of-concept, we implement a 28-GHz TX front-end using cascode PAs, based on the inverse outphasing architecture. In the measurement, the TX achieves 22.7-dBm saturated output power with 42.6% PA drain efficiency. The TX exhibits effective PA efficiency enhancement at 6-dB power back-off (PBO), validating the high-efficiency inverse outphasing active load modulation. Modulation tests with high-order quadrature amplitude modulation (QAM) signals demonstrate that the TX supports >10-Gb/s high-fidelity complex signals and achieves the state-of-the-art modulation performance.

Design of a Ka-Band Cascode Power Amplifier Linearized With Cold-FET Interstage Matching Network

A Ka-band CMOS cascode power amplifier (PA) linearized with a cold-FET-based interstage matching network is presented, which is designed in a 65-nm CMOS process. Since it is difficult to make a cascode PA matched to the optimum output and input impedances at high frequencies, a matching network has to be introduced at the node between the common-source (CS) and common-gate (CG) stages. The cold-FET-based matching network improves the linearity and the input and output impedance matchings, which is analyzed and optimized with its simple model. It makes the PA have gain expansion and phase lag with the power, which allows the PA to have less amplitude-to-amplitude (AM-AM) and amplitude-to-phase (AM-PM) distortions. In addition, it improves the return losses of the PA by making the impedances for power matching and conjugate matching located closely. The implemented PA achieves the peak power-added efficiency (PAE) of 38.2% and the saturated output power (P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sat</sub> ) of 17.1 dBm at 31 GHz while occupying the chip area of 0.16 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . It is also shown that the OP1 dB is improved by 1.7 dB, and the AM-PM distortion is reduced to only 1.1° due to the linearization technique. It is tested with 64-quadrature amplitude modulation (QAM) signals, which has a 400-MHz channel bandwidth (BW) and a 9.7-dB peak-to-average power ratio (PAPR). It achieves average output powers of 9.6/7.7 dBm with error vector magnitudes (EVMs) of -25/-30 dB for 64-QAM OFDM signals, efficiencies of 17.7%/12%, and the adjacent channel leakage ratio (ACLR) of -28.2/-32.8 dBc, respectively.

28-GHz CMOS Power Amplifier Linearized With Resistive Drain-Body Connection

A 28-GHz two-stage differential cascode power amplifier (PA) linearized with a simple common-source (CS) body network, in which the body of the CS amplifier at the power stage is connected to the drain through a large resistance. The body network is very simple but very effective to linearize the PA. The linearity improvements are explained and shown with the intermodulation distortions (IMD3) and AM-PM characteristics. The PA also shows a wideband gain because the matching networks consist mainly of transmission-line transformers (TLTs) and distributive interstage matching. It has a gain of 20.1 dB with a bandwidth of 10.8 GHz, a saturation output power of 20.25 dBm, and an output 1-dB compression point of 18.3 dBm, which is fabricated in a 40-nm bulk CMOS process with the area of 0.214 mm 2 .

220–360-GHz Broadband Frequency Multiplier Chains (x8) in 130-nm BiCMOS Technology

This article presents two broadband frequency multiplier chains (FMCs) fabricated with a standard 130-nm SiGe BiCMOS process. In both solutions, a broadband push-push frequency doubler (x2) operating at 220-360 GHz was employed. In order to properly drive such a doubler, with sufficient input power and bandwidth, two different power amplifiers (PAs) have been adopted: the former is based on a cascode configuration and the latter is based on a stacked topology. In addition, a D-band frequency quadrupler (x4) has been integrated before the PAs and doubler, to complete the design of frequency eighth tupler (x8) chains. The first FMC with the cascode PA achieves peak output power of 2.3 dBm, with maximum conversion gain (G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</sub> ) and bandwidth of 15 dB and 127 GHz, respectively. The second FMC with the stacked PA delivers a saturated output power of 2.5 dBm, with a maximum G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</sub> and a bandwidth of 12 dB and 72 GHz, respectively. The two FMCs consume maximum dc power of 0.537 and 0.542 W. The complete design procedure of the FMCs is presented in this article. To the best of our knowledge, the reported bandwidth is state-of-the-art and widest among SiGe based FMCs.

180 GHz high‐gain cascode power amplifier in a 130 nm SiGe process

A positive feedback gain-enhanced technique for power amplifiers has been introduced in this Letter. With the proposed circuit design method for optimal inductive feedback, a 180 GHz high-gain single-stage cascode power amplifier in a 130 nm SiGe process is implemented. The measurement results show a power gain of 10 dB and 20 GHz bandwidth with 110 mW dc power are achieved, and 6.5 dBm of output power referred to P 1dB and 3.5% collector efficiency are attained. The chip area of the power amplifier is only 0.50 × 0.48 mm2.

A 4.2-to-5.4 GHz stacked GaAs HBT power amplifier for C-band applications

PurposePower amplifiers (PAs) play an important role in wireless communications because they dominate system performance. High-linearity broadband PAs are of great value for potential use in multi-band system implementation. The purpose of this paper is to present a cascode power amplifier architecture to achieve high power and high efficiency requirements for 4.2∼5.4 GHz applications.Design/methodology/approachA common emitter (CE) configuration with a stacked common base configuration of heterojunction bipolar transistor (HBT) is used to achieve high power. T-type matching network is used as input matching network. To increase the bandwidth, the output matching networks are implemented using the two L-networks.FindingsBy using the proposed method, the stacked PA demonstrates a maximum saturated output power of 26.2 dBm, a compact chip size of 1.17 × 0.59 mm2 and a maximum power-added efficiency of 46.3 per cent. The PA shows a wideband small signal gain with less than 3 dB variation over working frequency. The saturated output power of the proposed PA is higher than 25 dBm between 4.2 and 5.4 GHz.Originality/valueThe technology adopted for the design of the 4.2-to-5.4 GHz stacked PA is the 2-µm gallium arsenide HBT process. Based on the proposed method, a better power performance of 3 dB improvement can be achieved as compared with the conventional CE or common-source amplifier because of high output stacking impedance.

A high power CMOS cascode power amplifier with adaptive dynamic bias control for linearity enhancement

AbstractThis work presents both high power and high linearity CMOS cascode power amplifier (PA) with adaptive dynamic bias (ADB) circuit. The ADB circuit sets appropriate gate bias for the common source and common gate (CG) amplifiers according to the input envelope signal, significantly improving the linearity. Meanwhile, harmonic termination circuits are introduced at the gate of the CG amplifier and the center‐tap node of the output transformer to short the second harmonic component to ground, further improving the linearity. In addition, this work utilizes an on‐chip series‐connected transformer‐based power combiner to enhance output power. A fully integrated differential PA including the ADB circuit is fabricated in 0.13 μm radio frequency silicon‐on‐insulator technology. From 2.5 V supply voltage, the proposed PA produces a saturated output power of 30.3 dBm with a peak power‐added efficiency of 43.1%. Thanks to the linearization techniques, the proposed PA transmits 23.5 dBm average linear output power with 3% error vector magnitude for a 20‐MHz 64‐QAM orthogonal frequency division multiplexing modulated signal without any digital predistortion circuits.

A 20-GHz Bandwidth Power Amplifier for Phased Array 5G New Radio Transmitters

A 27–47-GHz differential cascode power amplifier for millimeter-wave 5G new radio applications is presented. The PA is a three-stage design using inductively coupled impedance transformers with 31-dB nominal power gain. A device periphery ratio of 1:2:6 is adopted for predriver, driver, and final stage, respectively. A gain equalization technique was used in the interstage transformers to obtain the required bandwidth with high gain flatness. To enable the use of 2.7-V supply, a cascode topology was employed in all three stages. A small signal gain of 31 dB was achieved with a 3-dB bandwidth of 20 GHz, equivalent to a 54% fractional bandwidth centered at 37 GHz. A saturated output power of 20.6 dBm was measured at 38.5 GHz. With a 100-MHz 64-QAM OFDM modulated signal at 37 GHz and at EVM = −25 dB, an output power of 11.6 dBm and an ACLR1 of −32/−30.8 dBc were obtained. An SiGe HBT BiCMOS process with $f_{\mathrm{ MAX}} = 330$ GHz was used for fabrication. The PA has an active area of 0.28 mm2 and is measured to a best in class FOM of 94.7 dB.

Broadband InGaP/GaAs HBT Power Amplifier Integrated Circuit Using Cascode Structure and Optimized Shunt Inductor

This article presents a broadband two-stage cascode power amplifier integrated circuit (PAIC) using a 2- $\mu \text{m}$ InGaP/GaAs heterojunction bipolar transistor process. Since higher supply voltage of cascode power amplifier (PA) results in lower impedance transformation ratio of the matching network due to lower current, cascode PAs generally have broader bandwidth than common-emitter (CE) PAs. However, bandwidth analysis for handset PAs with a single-section load matching network, including transistors output capacitance, revealed that cascode PAs had bandwidth similar to CE PAs. Through bandwidth analysis based on power and efficiency contours at the internal plane of the transistor, an optimized shunt inductor with a single-section load matching network was proposed in this article to increase the bandwidth of cascode PA. Performances of both cascode and CE PAs with and without the optimized shunt inductor were compared. A broadband two-stage cascode PAIC with a compensating shunt inductor and an L-section matching network was designed and implemented. The implemented PAIC exhibited an output power of at least 30.1 dBm at frequency band ranging from 1.55 to 2.65 GHz for continuous-wave excitation. Using a long-term evolution signal with a peak-to-average power ratio of 7.5 dB and a signal bandwidth of 10 MHz, a power gain of more than 23.7 dB, power-added efficiency of 30.9% to 38.4%, and average output power of 26.7 to 27.7 dBm were obtained at a given adjacent channel leakage power ratio of −30 dBc. A fractional bandwidth was calculated to be 54.3% based on measured results.

D-Band and G-Band High-Performance GaN Power Amplifier MMICs

In this article, we present a set of gallium nitride (GaN) power amplifiers (PAs) that provide state-of-the-art performance within the D-band (110–170 GHz) and G-band (140–220 GHz) frequencies. A four-stage cascode PA operates with more than 25 dB of small-signal gain over a 107–148-GHz band. At 120 GHz, it can deliver up to 26.4 dBm of output power and up to 16.5% of power-added efficiency (PAE) with more than 26 dB of gain at saturation. The combination of these parameters is among the best reported with a solid-state technology at such high frequencies. The two G-band circuits are able to provide up to 40 GHz of 3-dB bandwidth and gain exceeding 10 dB up to 190 GHz. The measured peak output power is 15.8 dBm at 181 GHz in 0.6-dB gain compression with a corresponding PAE of 2.4%. To the best of our knowledge, these amplifiers show the highest gain above 170 GHz and the highest output power above 150 GHz among any reported GaN-based MMICs.