Cascode GaN HEMT Research Articles

An RC snubber design method to achieve optimized switching noise‐loss trade‐off of cascode GaN HEMTs

AbstractThe cascode gallium nitride high electron mobility transistors (GaN HEMTs) are very vulnerable to self‐sustained turn‐off oscillation due to their cascode configuration. This paper presents a design approach for the RC snubber of cascode GaN HEMTs to achieve the optimized noise‐loss trade‐off. At first, an analytical model is proposed to describe the instability of cascode GaN HEMTs‐based test circuits utilizing RC snubber. Based on the model, an analytical approach is proposed to achieve two optimum RC snubber designs S1 and S2. The design S1 can satisfactorily dampen the oscillation with minimum switching losses. The design S2 achieves maximum effective damping on the oscillation at a minimized cost of additional power losses. In the end, the accuracy of the proposed model is validated by the double‐pulse test and good agreement is obtained.

Analysis of the Influence of Temperature on Stress Waves of Cascode GaN HEMT

Analysis of the Influence of Temperature on Stress Waves of Cascode GaN HEMT

Degradation of electrical performance and radiation damage mechanism of cascode GaN HEMT with 80 MeV proton

In this paper, proton irradiations on Cascode GaN HEMT power device with an energy of 80 MeV and fluences of 2 × 1011 p/cm2 and 6 × 1011 p/cm2 have been carried out, where the threshold voltages drifted negatively by 20.55% and 28.17%, respectively. After two months of room temperature annealing, the threshold voltages recovered 0.22 V and 0.27 V, respectively. The ionizing deposition energy (IEL) was simulated by using Monte Carlo software and TCAD, it the results showed that the value of IEL in Si MOSFET is 5 ∼ 6 orders higher than that in GaN HEMT, while the value of the non-ionizing energy loss (NIEL) is one order higher than that in GaN HEMT. It means that the proton irradiation on the Cascode depleted GaN HEMT is more prone to produce displacement damage. As a large number of electrons and holes pairs were existed on the incident path of Si MOSFET under the proton irradiation, the produced electron will be captured by the gate oxide traps at the SiO2/Si interface, and the holes be captured by the defects generated in displacement damage, resulting in the accumulation of oxide trapped charges. Then, the electrical performance of Si MOSFET degrades seriously, thereby affecting the performance of the entire device. The studies will be helpful for the radiation hardening of Cascode GaN HEMT.

Ferrite Beads Design to Improve Turn-Off Characteristics of Cascode GaN HEMTs: An Optimum Design Method

In this paper, an optimum ferrite beads design method is proposed to suppress the self-sustained turn-off oscillation of cascode gallium nitride high-electron-mobility transistors (GaN HEMTs). At first, the impacts of gate loop beads and power loop beads on the turn-off oscillation of cascode GaN HEMTs are analyzed. The analysis reveals the weak damping effect of gate loop beads on the turn-off oscillation. Next, an analytical method is proposed to design the power loop beads that can achieve maximum effective damping on the turn-off oscillation. The power loop beads introduce extra stray inductance in the power loop, which can induce high voltage overshoot. To tackle the problem, an optimum design method is proposed so that the power loop beads can suppress the oscillation while mitigating the voltage overshoot. The accuracy of the proposed model is validated by the experimental data in the end.

Self-Sustained Turn-OFF Oscillation of Cascode GaN HEMTs: Occurrence Mechanism, Instability Analysis, and Oscillation Suppression

This article presents a comprehensive study on the occurrence mechanism, instability analysis, and suppression methods of self-sustained turn- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</small> oscillation, which occurs on cascode gallium nitride high electron mobility transistors (cascode GaN HEMTs). In the beginning, the oscillation waveforms are analyzed, which indicate that the occurrence of the oscillation is determined by test circuit instability. Based on the double pulse test, the impact of the load current <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$I_L$</tex-math></inline-formula> , dc bus voltage <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$V_{\text{DC}}$</tex-math></inline-formula> and gate resistance <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$R_{G}$</tex-math></inline-formula> on the self-sustained oscillation is identified. To investigate the instability of the resonant circuit, a small-signal ac model of the resonant circuit is derived. Based on the model, the influences of various parameters on the self-sustained oscillation are analyzed. The analyses reveal the possible methods which can suppress the oscillation. The effectiveness of the proposed methods is validated by the experimental data and simulation results in the end.

Electrical characterization of a 1200V GaN HEMT at cryogenic temperatures

The cryogenic operation of power converters integrated with the superconducting electric machines can leverage the lower parasitic, lower core material, and insulation requirement to reduce weight and increase power density in aerospace applications. To that end, Gallium Nitride High Electron Mobility Transistor (GaN HEMT) has recently proven to be the most viable option for the cryogenic converter operation. However, the topology selection and optimization are greatly influenced by the current/voltage rating of the power devices. Although series connected HEMTs can increase the blocking voltage, the dynamic voltage imbalance issue stemming from device parameter fluctuations, the larger number of required isolated gate driver makes the need for single high blocking voltage devices more compelling. This is even more pronounced in GaN due to its higher operating frequency which stems from the lower input capacitance. Although 900V cascode GaN HEMTs are now commercially available, single-chip high voltage HEMTs are attractive due to their zero reverse recovery charge, and lower package bonding parasitics. In this paper, a 1200V enhancement-mode GaN HEMT from GaNPower International has been characterized at cryogenic temperature. A 63% decrease has been demonstrated in the on-resistance, Rds(on) from room temperature to -150°C. The threshold voltage shows a 1.2x increase from room temperature to cryogenic temperature (-178°C). The transconductance (Gfs) shows a 1.34x increase for a temperature difference of 175°C. The results translate to a lower conduction loss and a faster switching speed and unfold further possibility of GaN in cryogenic converter applications.

A Review of Switching Oscillations of Wide Bandgap Semiconductor Devices

Wide bandgap (WBG) devices offer the advantages of high frequency, high efficiency, and high power density to power converters due to their excellent performance. However, their low parasitic capacitance and fast switching speed also make them more susceptible to switching oscillations. The switching oscillations can cause voltage and current overshoots, shoot-through, electromagnetic interference, additional power loss, and even device damage, which can seriously affect the performance of power converters and systems. However, a comprehensive and in-depth overview is lacking on this topic. This article reviews the types, the causes and negative effects, the effects of parasitic parameters and suppression methods of these switching oscillations, which is helpful for practical engineering. First, the switching oscillations are divided into different types, and their causes and negative effects are reviewed. Then, the effects of different parasitic parameters on the switching oscillations are overviewed. It is found that due to the different physical structures of silicon carbide metal-oxide-semiconductor field-effect transistors, enhancement-mode gallium nitride high-electron mobility transistors (eGaN HEMTs), and cascode GaN HEMTs, the effects are also different. Finally, the main methods of suppressing the switching oscillations are summarized, and the advantages and disadvantages of these methods are presented. Furthermore, future research works on this topic and the conclusion of this paper are drawn, which will help readers deepen their understanding of the switching oscillations of WBG devices, and inspire readers to better use WBG devices for high-frequency and high-efficient power conversion.

Simplified analytical model for estimation of switching loss of cascode GaN HEMTs in totem-pole PFC converters

A practical analytical model to calculate the switching loss of cascode gallium nitride high electron mobility transistors (GaN HEMTs) is proposed. To facilitate analysis and application, the transmission delays introduced by Si MOSFET and interconnection inductances are ignored in modeling. Meanwhile, the nonlinear junction capacitances of the device and circuit stray inductances are also incorporated to increase the accuracy of the model. The turn-on and turn-off switching processes are described in detail and the simplified equations can be easily solved by using mathematical tools. Based on the analytical model, loss evaluation of totem-pole PFC converter is introduced briefly. Finally, the accuracy of the model is validated by comparing the calculated loss and converter's efficiency with experiment results. Peak efficiency of 99.26% is achieved for a 3.6 kW single phase CCM Totem-Pole PFC AC/DC converter switching at 50 kHz based on 650 V cascode GaN HEMTs.

Paralleled Operation of High-Voltage Cascode GaN HEMTs

Paralleling devices is an effective way to achieve a higher power application while still having the convenience of using discrete devices. However, the mechanisms of potential failures and the circuit design considerations have not been thoroughly studied yet, when paralleling gallium nitride high-electron-mobility transistors (GaN HEMTs) in cascode configuration. This paper presents a comprehensive study of paralleled high-voltage cascode GaN HEMTs, evaluating both circuit design and device characteristics. The mechanisms of current oscillation, which occurred during the cascode GaN HEMT parallel operation, are analyzed in detail. The Q3D tool and Spice-based simulation model jointly quantify the sensitivity of the circuit parasitic parameters and the cascode GaN HEMT mismatches during the paralleled operation. General design guidelines are provided in the paper as well. A group of experimental results ultimately validate the analysis toward parallel operation.

&gt;70% Power-Added-Efficiency Dual-Gate, Cascode GaN HEMTs Without Harmonic Tuning

We report the state-of-the-art performance of deep-submicrometer gate length dual-gate GaN HEMTs and cascode GaN HEMTs with $10\times $ reduced gate-to-drain feedback capacitance compared with single-gate GaN HEMTs. With 150-nm gate length field-plated gate structures, these GaN HEMTs demonstrated improvement of small-signal gain by 10 dB, compared with single-gate GaN HEMTs. Large-signal load-pull measurements showed peak power-added-efficiency (PAE) of 71%–74% without harmonic tuning at 10 GHz, up to a measured continuous-wave output power level of 2.3–2.5 W. The 74% PAE is very close to a theoretical maximum PAE of 78.5% without harmonic tuning. Compared with single-gate GaN HEMTs, both the dual-gate and cascode GaN HEMTs offer $\sim 10$ % improvement in peak PAE at the output power of 2.3–2.5 W.

Cascode GaN HEMT를 적용한 위상 천이 dc-dc 컨버터의 구현 및 문제점 분석

Gallium nitride high-electron mobility transistor (GaN HEMT) is the strongest candidate for replacing Si MOSFET. Comparing the figure of merit (FOM) of GaN with the state-of-the-art super junction Si MOSFET, the FOM is much better because of the wide band gap characteristics and the heterojunction structure. Although GaN HEMT has many benefits for the power conversion system, the performance of the power conversion system with the GaN HEMT is sensitive because of its low threshold voltage () and even lower parasitic capacitance. This study examines the characteristics of a phase-shifted full-bridge dc-dc converter with cascode GaN HEMT. The problem of unoptimized dead time is analyzed on the basis of the output capacitance of GaN HEMT. In addition, the printed circuit board (PCB) layout consideration is analyzed to reduce the negative effects of parasitic inductance. A comparison of the experimental results is provided to validate the dead time and PCB layout analysis for a phase-shifted full-bridge dc-dc converter with cascode GaN HEMT.

Evaluation and Application of 600 V GaN HEMT in Cascode Structure

Gallium nitride high electron mobility transistor (GaN HEMT) has matured dramatically over the last few years. A progressively larger number of GaN devices have been manufactured for in field applications ranging from low power voltage regulators to high power infrastructure base-stations. Compared to the state-of-the-art silicon MOSFET, GaN HEMT has a much better figure of merit and shows potential for high-frequency applications. The first generation of 600 V GaN HEMT is intrinsically normally on device. To easily apply normally on GaN HEMT in circuit design, a low-voltage silicon MOSFET is in series to drive the GaN HEMT, which is well known as cascode structure. This paper studies the characteristics and operation principles of a 600 V cascode GaN HEMT. Evaluations of the cascode GaN HEMT performance based on buck converter at hard-switching and soft-switching conditions are presented in detail. Experimental results prove that the cascode GaN HEMT is superior to the silicon MOSFET, but it still needs soft-switching in high-frequency operation due to considerable package and layout parasitic inductors and capacitors. The cascode GaN HEMT is then applied to a 1 MHz 300 W 400 V/12 V LLC converter. A comparison of experimental results with a state-of-the-art silicon MOSFET is provided to validate the advantages of the GaN HEMT.