Cascaded Multilevel Inverter Research Articles

Design and Experimentation of Boost Cascaded DC Link Inverter for Domestic UPS Applications

A new structure of Boost Cascaded DC Link H-Bridge Inverter (BCDCLHBI) is proposed for domestic UPS applications. It consists of DC-DC converter, sub-multilevel modules and H-bridge inverter circuits. The proposed sub-multilevel modules synthesize a stepped DC link voltage with reduced voltage stress across the H-bridge inverter. Compared with conventional two-level inverter the proposed stepped DC link inverter configuration has reduced Power Spectral Density (PSD) and reduced voltage stress. Compared with conventional Cascaded Multilevel Inverter (CMLI) configuration, the proposed system has reduced power switches, DC sources and gate driver requirements. To obtain better quality of AC power output, carrier-level shifted Pulse Width Modulation (PWM) schemes are developed for sub-multilevel switching. A simulation and prototype model of 7-level BCDCLHBI is developed and its performance is validated.

Employing Multi-Phase DG Sources as Active Power Filters, Using Fuzzy Logic Controller

By placing distributed generation power sources beside a big nonlinear load, these sources can be used as a power quality enhancer, while injecting some active power to the network. In this paper, a new scheme to use the distributed generation power source in both operation modes is presented. In this scheme, a fuzzy controller is added to adjust the optimal set point of inverter between compensating mode and maximum active power injection mode, which works based on the harmonic content of the nonlinear load. As the high order current harmonics can be easily rejected using passive filters, the DG is used to compensate the low order harmonics of the load current. Multilevel transformerless cascade inverters are preferred in such utilization, as they have more flexibility in current/voltage waveform. The proposed scheme is simulated in MATLAB/SIMULINK to evaluate the circuit performance. Then, a 1kw single phase prototype of the circuit is used for experimental evaluation of the paper. Both simulative and experimental results prove that such a circuit can inject a well-controlled current with desired harmonics and THD, while having a smaller switching frequency and better efficiency, related to previous 3-phase inverter schemes in the literature.

Applying Selective Harmonic Elimination in Cascaded Multilevel Inverter using Cuckoo Algorithm

Applying Selective Harmonic Elimination in Cascaded Multilevel Inverter using Cuckoo Algorithm

Phase-Shifted Carrier Pulse Width Modulation Based on Particle Swarm Optimization for Cascaded H-bridge Multilevel Inverters with Unequal DC Voltages

High-voltage cascaded H-bridge multilevel (CHBML) inverters usually include many isolated dc voltage sources. Some dc source faults result in a drop in the dc voltage, thereby leading to unequal cell dc voltages. On the other hand, the differences in cell dc source parameters result in unequal dc voltages too. At present, riding through the faults of dc sources and operating under the condition of unequal dc voltages are required to improve the reliability of CHBML inverters. Unfortunately, the conventional phase-shifted carrier pulse width modulation (PSCPWM), which is widely used for CHBML inverters, cannot eliminate low-frequency sideband harmonics when cell dc voltages are not equal. This paper analyzes the principle of sideband harmonic elimination, and proposes an improved PSCPWM based on the particle swarm optimization algorithm. This modulation technique eliminates low-frequency sideband harmonics by calculating and regulating the carrier phases according to different cell dc voltages. The proposed PSCPWM enhances the reliability of the CHBML inverter and extends the range of its application. Simulation and experimental results obtained from the prototype of the CHBML inverter verify the theoretical analysis and the achievements made in this paper.

Reduction of Switches and DC Sources in Cascaded Multilevel Inverter

Harmonics and increasing number of switches and DC sources for increasing level is the major issue in the cascaded multilevel inverter for the application of medium and high voltage power system applications. In this paper several new techniques are used to reduce the switches and DC sources, which overcome the disadvantages of cascaded multilevel inverter. The THD values for various levels (seven & nine) are compared with and without PWM technique.

An Energy Stored Quasi-Z-Source Cascade Multilevel Inverter-Based Photovoltaic Power Generation System

The quasi-Z-source cascade multilevel inverter (qZS-CMI) presents many advantages over conventional CMI when applied in photovoltaic (PV) power systems. For example, the qZS-CMI provides the balanced dc-link voltage and voltage boost ability, saves one-third modules, etc. However, the qZS-CMI still cannot overcome the intermittent and stochastic fluctuation of solar power injected to the grid. This paper proposes an energy stored qZS-CMI-based PV power generation system. The system combines the qZS-CMI and energy storage by adding an energy stored battery in each module to balance the stochastic fluctuations of PV power. This paper also proposes a control scheme for the energy stored qZS-CMI-based PV system. The proposed system can achieve the distributed maximum power point track for PV panels, balance the power between different modules, and provide the desired power to the grid. A detailed design method of controller parameters is disclosed. Simulation and experimental results verify the proposed system and the control scheme.

Reduction of Switches and DC Sources in Cascaded Multilevel Inverter

Reduction of Switches and DC Sources in Cascaded Multilevel Inverter

Analysis of Minimum Modulation for the 9-Level Multilevel Inverter in Asymmetric Structure

The main function of multilevel inverters is to synthesize a desired AC voltage output starting from several input levels of direct current voltage. There are several circuit topologies and modulation strategies to generate the desired output voltage of an inverter, among which stands out the traditional Sine Pulse Width Modulation (SPWM) technique with several variants. Phase Disposition (PD), Phase Opposition Disposition (POD) and, Alternate Phase Opposition Disposition (APOD); are presented considering switching frequencies, the spectrum of the output waveform of the inverter, and total harmonic distortion. In this paper, the SPWM techniques are studied due to its easy implementation and for being the most widely used family of multilevel converters, applied to the 9-level Asymmetrical Cascaded Multilevel Inverter (ACMLI) with the trinary structure, which is not a traditional case by means of a simulation environment.

Cascaded Multilevel Inverter of 11 Levels for RL Load with Reduced Distortion

Cascaded H-bridge multilevel inverter structure allows modularized circuit layout and packaging, but they are prone to high switching losses due to high switching frequency. This problem can be alleviated by reducing the number of semiconductor switches and decreasing the number of switching per cycle. To overcome the foresaid drawbacks, this paper presents an 11 level cascaded H-bridge inverter feeding RL load, with reduced switching losses and less harmonic distortion. The inverter output voltage can be shaped by having unequal voltage sources. With proper switching, number of levels can be increased thus reducing the harmonic distortion, meanwhile the number of switching are also to be optimized. The proposed asymmetrical H-bridge inverter uses lesser number of switches and switching.

25MW급 대용량 멀티레벨 인버터의 시뮬레이션 기반 손실해석과 출력특성 비교 분석

The multi-level inverters are highly efficient for high-power and medium-voltage AC driving applications, such as high-speed railway systems and renewable energy resources, because such inverters generate lower total harmonic distortion (THD) and electromagnetic interface (EMI). Lower switching stress occurs on switching devices compared with conventional two-level inverters. Depending on the multi-level inverter topology, the required components and number of switching devices are different, influencing the overall efficiency. Comparative studies of multi-level inverters based on loss analysis and output characteristic are necessary to apply multi-level inverters in high-power AC conversion systems. This paper proposes a theoretical loss analysis method based on piecewise linearization of characteristic curves of power semiconductor devices as well as loss analysis and output performance comparison of five-level neutral-point clamped, flying capacitor inverters, and high-level cascaded H-bridge multi-level inverters.

Three-Phase Asymmetric Multilevel Inverter Topologies with Better Charge Balancing

Cascaded H-bridge multilevel inverter is among the most preferred topology in solar systems. While traditional asymmetric cascaded H-bridge multilevel inverter is easy to achieve higher number of output voltage levels compared to traditional symmetric cascaded H-bridge multilevel inverter, charge balancing between the voltage sources remains a challenge for asymmetric cascaded H-bridge multilevel inverter. This drawback results in unsteady DC voltage levels due to unbalanced power drawn from each voltage sources. Besides that, in battery powered applications, unbalanced power drawn results in unequal discharged in the batteries. In this paper, two three-phase asymmetric cascaded H-bridge multilevel inverter topologies are proposed which offer easier in terms of modularity while maintaining the ease in charge balancing control. The performance of these two proposed topologies with charge balance control has been evaluated using PSIM software.

A New Symmetric Cascaded Multilevel Inverter Topology Using Single and Double Source Unit

In this paper, a new symmetric multilevel inverter is proposed. A simple structure for the cascaded multilevel inverter topology is also proposed, which produces a high number of levels with the application of few power electronic devices. The symmetric multilevel inverter can generate 2n+1 levels with a reduced number of power switches. The basic unit is composed of a single and double source unit (SDS-unit). The application of this SDS-unit is for reducing the number of power electronic components like insulated gate bipolar transistors, freewheeling diodes, gate driver circuits, dc voltage sources, and blocked voltages by switches. Various new algorithms are recommended to determine the magnitude of dc sources in a cascaded structure. Furthermore, the proposed topology is optimized for different goals. The proposed cascaded structure is compared with other similar topologies. For verifying the performance of the proposed basic symmetric and cascaded structure, results from a computer-based MATLAB/Simulink simulation and from experimental hardware are also discussed.

A New Cascaded Multilevel Inverter Topology with Voltage Sources Arranged in Matrix Structure

The paper unleashes a new idea to arrive at reduced switch count topological structures configured in the form of a matrix for a cascaded Multi level inverter (CMLI). The theory encircles to minimize the number of switches involved in the conduction path and there from acclaim reduced input current distortion, lower switching losses and electromagnetic interference. The focus extends to standardize the number of power devices required for reaching different levels of output voltage from the same architecture. It includes appropriate pulse width modulation (PWM) strategy to generate firing pulses and ensure the desired operation of the power modules. The investigative study carries with it MATLAB based simulation and experimental results obtained using suitable prototypes to illustrate the viability of the proposed concept. The promising nature of the performance projects a new dimension in the use of single phase MLIs for renewable energy related applications.

A New Reactive Current Reference Algorithm for the STATCOM System Based on Cascaded Multilevel Inverters

This paper presents a simple controller integrating a new reactive current reference algorithm for enhancing the transient performance of static synchronous compensator (STATCOM). A multilevel cascaded inverter with separated dc capacitors which is driven by carrier-based pulse width modulation is used to implement the STATCOM. The voltage across each dc-link capacitor is regulated by the rotated switching swapping scheme. In this paper, the STATCOM is controlled to provide both reactive power (VAR) compensation and grid power factor correction at the point of common coupling with a dynamically varying reactive load system. The proposed algorithm enhances the transient performance of the closed-loop system with only proportional controller and minimizes the STATCOM reactive current ripples. STATCOM based on a five-level cascaded inverter is presented in this paper and the performance of the proposed controller is investigated through various simulation studies using MATLAB/Simulink software for both steady state and transient conditions. A laboratory prototype is also developed to verify the simulation results where a good match between simulation and experimental results is achieved.

Phase Disposition PWM Technique for Eleven Level Cascaded Multilevel Inverter with Reduced Number of Carriers

Applying pulse width modulation (PWM) techniques for cascaded multilevel inverters are very complex for topologies with reduced number of switches. In this paper for phase disposition (PD) pulse width modulation technique a new algorithm is proposed and implemented on eleven level cascaded multilevel inverter under reduced switches topology. In the proposed algorithm instead of N-1 carrier waves, the required number of switching pulses generated by considering number of carrier waves is equal to number of switches. This technique allows lower switching transition and it leads to reduced switching losses for topologies utilize minimum number of switches. 1.2 KHz carrier frequency is used to generate switching pulses and verified up to 100 kHz. The Total harmonic distortion is observed for various switching frequencies. The obtained output voltage levels using PD PWM technique proved mathematically. The performance of proposed algorithm is evaluated using Matlab/Simulink. DOI: http://dx.doi.org/10.11591/telkomnika.v15i1.8076

Assessment of Single Phase Cascaded Multilevel Inverter using Equal and Unequal Amplitude Carriers

Assessment of Single Phase Cascaded Multilevel Inverter using Equal and Unequal Amplitude Carriers

A Study and Comparison of Cascaded Multilevel Inverters using GATES for Switching

A Study and Comparison of Cascaded Multilevel Inverters using GATES for Switching

Selective Harmonic Elimination in Asymmetric Cascaded Multilevel Inverters Using a New Low-frequency Strategy for Photovoltaic Applications

Asymmetric multilevel inverters with a main and auxiliary power circuit can yield maximum number of voltage levels against the number of semiconductor devices. Most of the output power will be produced by the main inverter, which works at low frequency and the auxiliary inverters only improve the voltage quality. Advantages of the asymmetric structure are reduced number of semiconductors and gate drive circuits and better voltage quality and efficiency, which make the asymmetric inverter to be a perfect candidate for photovoltaic applications. This article presents a new switching strategy in asymmetric multilevel inverters, which exploits extra degrees of freedom to eliminate more low-order harmonics. Simulation results show this method can introduce two new switching angles without affecting the power losses of the inverter.

Comparative Analysis of Cascadeded Multilevel Inverter for Phase Disposition and Phase Shift Carrier PWM for Different Load

This paper presents the optimized harmonic elimination stepped waveform technique to improve the output waveform of 7-level Cascaded Multilevel Inverter (CMLI) fed induction motor. The CMLI with separate DC source is used generate a 7-level output with three H-bridge and 12 switch's. The working of 7-level CMLI is analyzed by phase disposition and phase shifting pulse width modulation with bipolar and unipolar modes of operation. The performance of CMLI is examined by various parameters such as THD, power factor, motor current, motor speed and torque. The presented result carried out using MATLAB/simulink. The simulation result for phase disposition and phase shift carrier PWM were compared. The 7-level CMLI hardware with phase shift carrier modulation was developed to validate simulation result.

Hybrid Multicarrier Modulation to Reduce Leakage Current in a Transformerless Cascaded Multilevel Inverter for Photovoltaic Systems

This letter proposes a hybrid multicarrier pulse width modulation (H-MCPWM) technique to reduce leakage current in a transformerless cascaded multilevel inverter for photovoltaic (PV) systems. The transformerless PV inverter topology has the advantages of simple structure, low weight and provides higher efficiency. However, the topology makes a path for leakage current to flow through parasitic capacitance formed between the PV module and the ground. A modulation technique has significant impact to reduce the leakage current without adding any extra component. The proposed H-MCPWM technique ensures low leakage current in the transformerless PV inverter system with simplicity in implementation of the modulation technique using lesser number of carriers. Experimental prototype developed in the laboratory demonstrates the performance of the proposed modulation technique in reducing the leakage current.