Cascaded H-bridge Multilevel Inverter Topology Research Articles

A novel 7-level reduced-switch MLI topology fed PMSM drive for electric vehicle system

The compact and efficient design motivates the renewable energy-powered permanent magnet synchronous motor drive for electric vehicle applications. The available renewable energy is interfaced with a power drive by employing an electronic commutator such as a conventional 3-level inverter. But, the multilevel inverter produces favorable merits by producing staircase output voltage from several input direct current (DC) sources. The cascaded H-bridge multilevel inverter plays a significant role in many applications, but it was developed only for limited voltage levels. The major problem in cascaded h-bridge multilevel inverter (CHBMLI) requires more switching devices for higher voltage levels, which increases the size, cost and space of the electric vehicle (EV). To overcome above-mentioned problems, a new objective has been developed by employing the novel Reduced-switch multilevel inverter topology for higher voltage levels. This improves the voltage quality and reducing the harmonic level, and common-mode voltage issues. The main contribution of this work is, developing the novel 5-level, 7-level reduced-switch multilevel inverter (RSMLI) topologies with reduced switching devices with favourable merits over CHBMLI topology. Finally, the performance of proposed novel 5-level and 7-level RSMLI topologies fed PMSM drive for EV system has been verified, by using MATLAB/Simulink computing tool, and simulation results are presented with comparisons.

Evaluation of CHB MLI based shunt APF using low pass filter and self-tuning filter

The increasing demand for high-rating power supply in the distribution system causes the conventional inverter topology, six step voltage source inverter (SSVSI) unsuitable for being applied as active power filter (APF). Multilevel inverter (MLI) is generally the best suitable inverter for APF, but not all types of MLI can be used for high-voltage applications. Among the MLIs topology, cascaded H-bridge (CHB) is the best choice since it can produce output voltage more than twice the amount of DC source. Moreover, CHB MLI topology uses fewer power devices and is simple in design. Low pass filter (LPF) is a common method used for harmonic extraction in this controller. However, this method faces various problems, such as an additional need for phase lock loop (PLL) algorithm and slow transient and steady-state responses. Therefore, self-tuning filter (STF) is introduced as a new filtering method to overcome this problem. This paper evaluates CHB MLI's performance for APF using STF as a harmonic extraction. The model was developed and verified in MATLAB/Simulink. The results show that harmonic extraction using STF performs better total harmonic distortion (THD) than conventional LPF. Nevertheless, both algorithms produce THD below 5%, defined as the permissible value stated in IEEE 519.

Implementation of Two-Stage Multilevel Inverter System Using PIC Controller

In this study, the Cascaded H-Bridge Multilevel Inverter (CMLI) is described for use with infrared dryer loads. Because of the low harmonic distortion content and reduced voltage stress in the switching devices, CMLI is one of particular interest. The CMLI topology and the Selective Harmonic Elimination Pulsed Width Modulation (SHEPWM) technology were studied and evaluated. To evaluate the inverter, SHEPWM modulation was studied and applied. The system also includes a DC-DC converter. The converter was designed to be used in infrared drying system powered by direct current (DC) power where an increased output voltage is required. This study also presented an evaluation of performance using infrared load of the CMLI based on power used at 100 W. As a result, a comparison of input power was made, and an assessment into the converter's power quality in terms of harmonic content and overall efficiency was conducted. The implementation of the system by hardware had been able to reduce the harmonic to 15.5%.

Design of Cascaded H-Bridge Multilevel Inverter Topology for Integrated Portable Power Pack Application

This paper presents the necessity of portable power supplies that can be carried and cater to all the users' demands. Since the energy storage of the portable power pack are coming from DC supply, it needs an inverter to convert the DC voltage into AC voltage. Most of the low-priced inverters in the market have a simple build and are inefficient, resulting in high THD that can cause the electrical appliance not to work properly. This project was focused on the most suitable inverter type where the cascaded H-bridge multilevel inverter with PWM switching technique was proposed. This type of inverter will produce a better THD and a higher output voltage level when the inverter level is increased. This theory was proved where 3-level, 5-level and 7-level of Cascaded H-Bridge Multilevel Inverter has a 52.05 %, 29.98 % and 21.94 % of voltage THD. These results prove that by increasing the output voltage level can reduce the voltage THD. For the hardware implementation, a 5-Level Cascaded H-Bridge Multilevel Inverter with PWM switching technique is chosen because it has a lower voltage THD compared to 3-Level Cascaded H-Bridge Multilevel Inverter and at the same time use less of semiconductor devices compared to 7-Level Cascaded H-Bridge Multilevel Inverter and has fewer semiconductor losses compared to the inverter with SPWM switching technique. The voltage THD of circuit models hardware when reaches 24 V_pk is 28.3 % which is slightly better to simulation result, 29.98 %. This inverter was then connected with a step-up transformer with a ratio of 1:10 to reach standard electrical voltage supply in Malaysia of 230 V_rms with a voltage THD of 28.4 % without load and 30 % with load. This proves that the circuit model can work properly as the 5-Level Cascaded H-Bridge Inverter simulation and hardware results show a good agreement.

Evolutionary Metaheuristic Methods Applied to Minimize the THD in Inverters: A Systematic Review

In recent research works, metaheuristic methods have been widely used to minimize THD in inverters, these methods provide better computation time and effective results compared to classical methods. This paper presents a systematic analysis with a comprehensive coverage of metaheuristic methods applied to multilevel inverters. The search focused on the characteristics of the inverters used in the articles (topologies, levels, loads and evolutionary method). The aim is to show which are the characteristics of the most used case studies for the application of evolutionary metaheuristic methods. The IEEEXplorer, ScienceDirect, IET Digital Library, Springer and WorldWideScience databases have been used for the review since 2010. The results of the review show that many researchers use evolutionary algorithms, with Cascaded H-bridge Multilevel Inverter topology, RL loading and 7 levels. This highlights which features of the case studies are the most used and analysed to explore the advantages of using evolutionary metaheuristic methods.

PSO Based Selective Harmonic Elimination PWM for Cascaded H-Bridge Multilevel Inverter

A Single phase Cascaded H-bridge multilevel inverter topology fed by Photovoltaic source for the reduction of harmonics is proposed in this paper. Selective Harmonic Elimination technique is employed for elimination of 5th, 7th, 11th and 13th lower order harmonics and the particle swarm optimization algorithm is employed for estimating the switching angles. As a novelty, in order to maintain the power balance among the various sources, a cyclic selection procedure is adopted that over a period of operation also the sources equally contribute for the output power. MATLAB software is used for optimization and the results show the effectiveness of the proposed algorithm. The performance of the Particle Swarm Optimization Algorithm has been compared against the performance of the Genetic Algorithm.

THD analysis for symmetrical five level and seven level cascaded multilevel inverter

Total Harmonic Distortion (THD) is one of the problems in the multilevel inverter. This paper discussed a brief review of THD in different cascaded H-bridge multilevel inverter topologies of five levels and seven levels at the output waveforms. The five levels inverter contains eight switches while seven levels inverter used twelve switches. Each single H-bridge inverter circuit is fed by equally independent DC source for both inverters. The inverter uses MOSFET as the switching point and acts as the controller for a fundamental switching operation. The switching value has been set at the gating block to control the operation of the MOSFET switching. Several waveforms and simulation findings are provided to validate the quality of the proposed topology.

Medium Voltage Impedance-Admittance Measurement System Based on the Cascaded H-Bridge Multilevel Converter

Recent trends in power system design such as an increasing share of renewable energy sources and smart grids are creating different subsystem interactions that require proper investigation, understanding, describing and estimating global system stability through impedance-admittance measurement and identification. This paper proposes and presents the cascaded H-bridge multilevel inverter topology for perturbation injection converter and impedance-admittance measurement. The methodology of impedance-admittance measurement is explained together with different measurements requirements. Performance and suitability of this topology for impedance-admittance measurement is evaluated through simulations. Preliminary design principles are given for the converter. System level feasibility of the solution is proposed as a main result of the work.

Investigation of modified multilevel inverter topology for PV system

Multilevel inverters become an alternative for high power and medium voltage applications in recent years. Multilevel inverters(MLI) are basically classified as Diode Clamped Multilevel inverter, Flying Capacitor Multilevel inverter, Cascaded H Bridge Multilevel Inverter (CHBMLI). The CHBMLI topology which consists of a series of H bridge unit with separate dc sources is mostly prefered to generate higher voltage levels, as it requires fewer components compared to the other topologies. As the level increases, the switching device requirement will be more and the circuit becomes large with this topology. To overcome this and to produce high quality output, reduced switch count topologies are the main focus in recent research.The reduced switch count structures are based on bidirectional switches, modified form of the structures, polarity and level generation based structure, reduced switch structures and hybrid topology structure. This paper proposes a three phase Modified Multilevel Inverter (MMLI) topology with reduced switch count for nine level and the topology is analyzed using different Pulse Width Modulation (PWM) technique. The proposed MLI structure consists of an H bridge unit with voltage conversion cell for each phase. It requires 24 switches for a 3Ф nine level inverter with eight switches per phase compared to 48 switches in CHBMLI. The Total Harmonic Distortion (THD) level of this topology is examined with the PWM techniques for symmetric and asymmetric DC voltage sources. THD results of the proposed MLI are compared with other reduced switch topology structure. The comparison result indicates that the proposed topology shows better harmonic level and reduced switches compared to that structure. A prototype of the proposed topology is built and is tested to validate with the simulation results. Simulation and experimental results show that the proposed topology produces a minimum harmonic level with fewer components.

Neutral Point Clamped and Cascaded H-Bridge Multilevel Inverter Topologies – A Comparison

Objectives: This work emphasizes on the analysis of two five levels inverter topologies - neutral point clamped topology and Cascaded H-Bridge inverter topology. Methods/Analysis: The neutral point clamped topology requires only one DC source, eight switches and four clamping diodes with two voltage balancing capacitors. The cascaded topology carries two voltage sources and eight switching devices. Phase disposition pulse width modulation technique generates gating pulses for both the multilevel inverter topologies. All the simulations are done in MATLAB-Simulink simulation environment. Findings: The output waveforms, switching stress and harmonic spectrum of the output waveforms of both the inverter topologies are obtained using phase disposition pulse width modulation technique for a modulation index of unity. Moreover, the work aims to perform a comparison of both the inverter topologies with respect to total harmonic distortion, switch stress and complexity of the topology. It is found that though a cascaded inverter needs less overall components when compared to neutral point clamped inverter, yet both the inverter topologies carries the same stress across their switches and produce an almost the same harmonic distortion on their output waveforms. Applications/Improvement: Conventional voltage source inverters are gradually being replaced by multilevel inverters in various applications like photovoltaic systems, reactive power compensators, FACTS devices, adjustable speed drives etc. The stress across each of the switches gets decreased in both the multilevel inverter topologies compared to conventional inverters. Further, neutral point clamped inverters carry the advantage of requiring only one DC source for its operation.

Three-Phase Asymmetric Multilevel Inverter Topologies with Better Charge Balancing

Cascaded H-bridge multilevel inverter is among the most preferred topology in solar systems. While traditional asymmetric cascaded H-bridge multilevel inverter is easy to achieve higher number of output voltage levels compared to traditional symmetric cascaded H-bridge multilevel inverter, charge balancing between the voltage sources remains a challenge for asymmetric cascaded H-bridge multilevel inverter. This drawback results in unsteady DC voltage levels due to unbalanced power drawn from each voltage sources. Besides that, in battery powered applications, unbalanced power drawn results in unequal discharged in the batteries. In this paper, two three-phase asymmetric cascaded H-bridge multilevel inverter topologies are proposed which offer easier in terms of modularity while maintaining the ease in charge balancing control. The performance of these two proposed topologies with charge balance control has been evaluated using PSIM software.

Charge Balancing Control for an Asymmetric Multilevel Inverter with Multiple Paired-H-Bridges

Cascaded H-Bridge (CHB) multilevel inverter (MLI) is among the most preferred topology in solar PV systems. While traditional asymmetric CHB MLI is easy to achieve higher number of output voltage levels compared to traditional symmetric CHB MLI, charge balancing between the voltage sources remains a challenge for asymmetric CHB MLI. This drawback results in unsteady DC voltage levels due to unbalanced power drawn from each voltage sources. Besides that, in battery powered applications, unbalanced power drawn results in unequal discharged in the batteries. In this paper, an asymmetric CHB MLI topology is proposed which is easier to modularize as for symmetric CHB MLI while maintaining the ease in charge balancing control. The performance of this proposed asymmetric CHB MLI with charge balance control has been evaluated using PSIM software.

New Modified Cascaded H-Bridge Multilevel Inverter Topology with Reduced Switches

Multilevel Inverter widely used in high power industrial applications. This paper presents a new modified cascaded H-Bridge multilevel inverter with reduction of switching component. In traditional CHB inverters required more number of components, it seem to more complex control circuitry and bulky. Since Last few decade the researchers from all over world concentrating to improve the efficiency of Multilevel Inverter such as voltage balancing, reduction in components, modulation methods and control technique etc. The Proposed multilevel inverter output voltage level increasing by using less number of switches driven by the multicarrier modulation techniques. In this paper presents generalized structure, Operation, comparison with other traditional topology, Simulation results with MATLAB/SIMULINK and experimental results.

New Cascaded H-Bridge Multilevel Inverter Topology with Reduced Number of Switches and Sources

In this paper mainly focused on the design and implementation of new topology in a single phase five level cascaded H-bridge multilevel inverter by using only a five switches and two DC power source. The main objective of this paper is to increase number of levels with a low number of switches and sources at the output without adding any complexity to the power circuit. The main merit of the new topology is to reduce the lower total harmonic distortion, lower electromagnetic interference generation and high output voltage. In this paper, various carrier pulse width modulation techniques are proposed, which can minimize the total harmonic distortion and enhances the output voltages from proposed work of five level inverter. The various switching topologies of single-phase five level cascaded H-bridge multilevel inverters have been analyzed in this paper. It is justified that the new topology can be recommended to single phase five level Cascaded H-bridge inverter for better performance in comparison with conventional method. The simulation is done by Mat Lab 8.0 version software.

An energy optimized control scheme for a transformerless DVR

The dynamic voltage restorer (DVR) is considered as the most effective and economic solution for voltage disturbances. This paper presents an energy optimized control scheme for a transformerless DVR. The DVR structure is based on a cascaded H-bridge multilevel inverter topology to eliminate the need of insertion transformers. The proposed control algorithm maintains a balanced load-side voltage even during the compensation of unbalanced disturbances with a minimum active power injection. Moreover, the proposed scheme maximizes the ride-though capability of the DVR during voltage sags. This feature is verified by using capacitors instead of dc sources as energy storage elements for the DVR. Furthermore, the proposed minimum energy scheme prevents the rise in the dc-side voltage of the inverter when compensating voltage swells. The performance of the proposed DVR system is evaluated for compensating different types of voltage disturbances. The results validate the robustness and the accuracy of the proposed system.