Cascade Topology Research Articles

Novel Topologies for Symmetric, Asymmetric, and Cascade Switched-Diode Multilevel Converter With Minimum Number of Power Electronic Components

In this paper, novel topologies for symmetric, asymmetric, and cascade switched-diode multilevel converter are proposed, which can produce many levels with minimum number of power electronic switches, gate driver circuits, power diodes, and dc voltage sources. The number of required power electronic switches against required voltage levels is a very important factor in designing of multilevel converter, because switches define the reliability, circuit size, cost, installation area, and control complexity. For asymmetric and cascade converter, new algorithms for determination of dc voltage sources values are presented. To produce maximum number of levels at the output voltage, the proposed cascade topology is optimized for different goals, such as the minimization of the number of power electronic switches, gate driver circuits, power diodes, dc voltage sources, and blocking voltage on switches. Comparison of the results of various multilevel converters will be investigated to reflect the merits of the presented topologies. The operations of the proposed multilevel converters have been analyzed with the experimental and simulation results for different topologies. Verification of the analytical results is done using MATLAB simulation.

Design of New Single-phase Multilevel Voltage Source Inverter

Multilevel inverters with more number of levels can produce high quality voltage waveforms. In this paper, a new single-phase structure for multilevel voltage source inverter is proposed which can generate a large number of levels with reduced number of IGBTs, gate driver circuits and diodes. Three algorithms for determination of dc voltage sources’ magnitudes are presented which provide odd and even levels at the output voltage waveform. A comparison is presented between proposed multilevel inverter and conventional cascade topology. The proposed topology is analyzed by the experimental and simulation results. DOI: http://dx.doi.org/10.11591/ijpeds.v5i1.6218

A NOVEL ARTIFICIAL HYDROCARBON NETWORKS BASED SPACE VECTOR PULSE WIDTH MODULATION CONTROLLER FOR INDUCTION MOTORS

Most of machine-operated industrial processes imple ment electric machinery as their work sources, implying the necessary improvement of control techniques and power electronics drivers. Many years hav e passed since the control conflicts related to induc tion motors have been overcome through torque-flux control techniques so their advantages over direct current motors have made them to be the most common electric actuator found behind industrial automatio n. In fact, induction motors can be easily operated using a Direct Torque Control (DTC). Since, it is based on a hysteresis control of the torque and flux errors, its performance is characterized by a quick reaching of the set point, but also a high ripple on both torq ue and flux. In order to enhance that technique, this stud y introduces a novel hybrid fuzzy controller with a rtificial hydrocarbon networks (FMC) that is used in a Space Vector Pulse Width Modulation (SVPWM) technique, so-called FMC-SVPWM-DTC. In fact, this study describes the proposal and its design method. Experimental results over a velocity-torque cascade topology proved that the proposed FMC-SVPWM-DTC responses highly effective almost suppressing rippl ing in torque and flux. It also performed a faster speed response than in a conventional DTC. In that sense, the proposed FMC-SVPWM-DTC can be used an alternative approach for controlling induction moto rs.

Invulnerability Analysis of Large Logistics Supply Chain Network in Complex Environment Based on the Internet of Things

The network cascade topology structure of large logistics supply chain and its invulnerability were researched. Logistics supply chain is the combination set of entities such as warehouse, highway, railway, aviation, etc. And its stability of network structure determined the survival and development of the user in the network and supply chain. In order to improve the stability and robustness of logistics supply chain network, an improved cascaded topology structure of large logistics supply chain network with Internet of things in complex environment was proposed based on metric uniform random distribution, and cascading invulnerability of mathematical analysis model was proposed. The probability distribution and critical value of logistics and supply chain network cascading failure was solved in complex environment, and the logistics supply chain network paralysis and damage problems were analyzed from the view of probability and critical value analysis. Take the intelligent car supply chain as the example, simulation result shows that the invulnerability analysis effect is perfect, and the cascading invulnerability critical value is solved precisely, research results provide important theoretical support to realize the intelligent logistic management, it has good application value in the research of logistics supply chain network security and stability.

A Ku-Band Low Noise Amplifier Based on Transformer

The aim of this paper is to design and implement a low noise amplifier (LNA) based on transformer for a Ku-band application. The proposed CMOS LNA can have an enhanced gain because of the cascade topology, a highly flat gain response because of the RC feedback network, and a wide passband because of the source degeneration structure that effectively suppresses the Miller effect. The Ku-band LNA dissipates 22.175 mW power and achieves the S11 of -10.31 to -6.77 dB, S22 of -18.1 to -37.78 dB, flat S21 of 8.78 to 10.59 dB, and noise figure of 3.96 to 5.33 dB across the 12~18 GHz span. The measured output P1dB is approximately -2 dBm. The chip size including all testing pads is only 0.545 x 0.599 mm2.

A 0.9V CMOS 3-5 Ghz broadband flat gain low-noise amplifier for ultra-wide band receivers

In this paper, a 3-5 GHz broadband flat gain low-noise amplifier (LNA) for ultra-wide band (UWB) receivers is presented. In this circuit, a cascode and cascade topology with modified input matching are designed in the frequency range of 3- 5 GHz. Choosing a common-gate technique presents greater flatness in broadband gain in the wide band frequency at the less than -3 dB input reflection coefficient. This approach allowed obtaining a flat broadband gain of 16.7±0.15 dB with an input reflection coefficient less than -5 dB, an output reflection coefficient less than -6 dB, and a noise figure less than 4.3 dB. It uses only 0.9 V voltage supply at 0.18 μm technology and consumes 13 mW (excluding buffer).

Cascade Dual Buck Inverter With Phase-Shift Control

This paper presents a new type of cascade inverter based on dual buck topology and phase-shift control scheme. The proposed cascade dual buck inverter with phase-shift control inherits all the merits of dual buck type inverters and overcomes some of their drawbacks. Compared to traditional cascade inverters, it has much enhanced system reliability thanks to no shoot-through problems and lower switching loss with the help of using power MOSFETs. With phase-shift control, it theoretically eliminates the inherent current zero-crossing distortion of the single-unit dual buck type inverter. In addition, phase-shift control and cascade topology can greatly reduce the ripple current or cut down the size of passive components by increasing the equivalent switching frequency. A cascade dual buck inverter has been designed and tested to demonstrate the feasibility and advantages of the system by comparing single-unit dual buck inverter, 2-unit and 3-unit cascade dual buck inverters at the same 1 kW, 120 V ac output conditions.

Inclusive search for same-sign dilepton signatures in pp collisions at $ \sqrt {s} = 7 $ TeV with the ATLAS detector

An inclusive search is presented for new physics in events with two isolated leptons (e or μ) having the same electric charge. The data are selected from events collected from pp collisions at $ \sqrt {s} = 7 $ TeV by the ATLAS detector and correspond to an integrated luminosity of 34 pb−1. The spectra in dilepton invariant mass, missing transverse momentum and jet multiplicity are presented and compared to Standard Model predictions. In this event sample, no evidence is found for contributions beyond those of the Standard Model. Limits are set on the cross-section in a fiducial region for new sources of same-sign high-mass dilepton events in the ee, eμ and μμ channels. Four models predicting same-sign dilepton signals are constrained: two descriptions of Majorana neutrinos, a cascade topology similar to supersymmetry or universal extra dimensions, and fourth generation d-type quarks. Assuming a new physics scale of 1 TeV, Majorana neutrinos produced by an effective operator V with masses below 460 GeV are excluded at 95% confidence level. A lower limit of 290 GeV is set at 95% confidence level on the mass of fourth generation d-type quarks.

Conceptual design of the power supply system for the in-vessel saddle coils for MHD control in ASDEX Upgrade

In the frame of an ASDEX Upgrade enhancement, a system of active in-vessel coils (of two types, dubbed “A” and “B”) and conducting wall for MagnetoHydroDynamic (MHD) stabilization is being designed and implemented. The conceptual design of the power supply (PS) system has been worked out and extensive analyses have been performed to verify that the identified basic modules, based on a cascade topology with two IGBT (Isolated Gate Bipolar Transistor) H-bridges in series for the A units and one H-bridge for the B ones, were able to fulfil all the requirements, well within semiconductors safety operating limits. The paper summarizes the work which led to the definition of the PS requirements, describes the topologies of the selected basic units and of the overall scheme, discusses the design choices and reports the results of the numerical simulations carried out to check the overall performance.

Design of variable gain low noise amplifier using feedback circuit with memory circuits for 5.2 GHz band

This paper presents a novel adaptive gain control method for Low Noise Amplifiers (LNAs) at the 5.2 GHz band using a feedback circuit, and operating in the baseband signal frequency. A uniform step variable gain can be implemented using a two-stage LNA based on the cascade topology. The feedback circuit consists of seven functional blocks, each of which has been designed for minimum power consumption. The storage circuit in the feedback circuit is used to store the previous signal magnitude, thus avoiding unnecessary power consumption in the LNA. We simulated the performances of LNA in terms of the gain, IIP3, Noise Figure (NF), stability, and power consumption. The adaptive front-end LNA with the feedback circuit can achieve a variable gain from 11.39 dB to 22.74 dB with excellent noise performance even at a high gain mode. The DC power of the proposed variable gain LNA consumes 5.68---6.75 mW under a 1.8 V supply voltage.

COMPACT, ULTRA-BROADBAND COPLANAR-WAVEGUIDE BANDPASS FILTER WITH EXCELLENT STOPBAND REJECTION

A compact, ultra-broadband coplanar-waveguide (CPW) bandpass fllter (BPF) is demonstrated. The proposed CPW-BPF is essentially designed by exploiting CPW short-stub and open-stub structures. Technically, the proposed fllter comprises shunt short- stub and series open-stub structures that are connected in a cascade topology. The higher and lower cutofi frequencies are mainly related to the electrical length of the shunt short stub and the series open stub, respectively. In addition, the stopband rejection is enhanced through an incorporation of CPW bandstop structures. The proposed fllter design is verifled through experimental demonstration. The corresponding lumped equivalent and transmission-line equivalent circuits are provided for circuit design purpose. Compared with the classical CPW-BPFs, the proposed fllter is of a relatively simple and compact conflguration. The demonstrated CPW-BPF has about 110% 3-dB fractional bandwidth, sharp selectivity, and great stopband rejection.

Further results in multiset processing with neural networks

This paper presents new experimental results on the variadic neural network (VNN) [McGregor, S. (2007). Neural network processing for multiset data. In Proceedings: Vol. 4668. Artificial neural networks - ICANN 2007, 17th international conference (pp. 460-470). Springer]. The inputs to a variadic network are an arbitrary-length list of n-tuples of real numbers, where n is fixed, and the function computed by the network is unaffected by permutation of the inputs. This paper describes improvements in the training algorithm for the variadic perceptron, based on a constructive cascade topology, and performance of the improved networks on geometric problems inspired by vector graphics. Further development may allow practical application of these or similar networks to vector graphics processing and statistical analysis.

A 5.15–5.35 GHz band 10 W power amplifier using SiC MESFETs

AbstractA 10 watt radio frequency power amplifier using commercially available silicon carbide (SiC) metal semiconductor field effect transistors (MESFETs), Cree CRF‐24010F, was designed. The frequency range covers 5.15 GHz to 5.35 GHz for using IEEE 802.11a Wireless Local Area Network (WLAN) applications. The 2nd and 3rd order harmonics cancellation technique was introduced to obtain high linearity. A cascade topology was employed to increase small signal gain, isolation, and stability throughout the bandwidth. At VDS1 = VDS2 = 48 V and IDS1 + IDS2 = 871 mA, 11 ± 1 dB power gain, 40 dBm (10 W) output power and 32.5% power added efficiency (PAE) over the operating bandwidth have been achieved in the two stage design. Two‐tone simulation at frequency spacing of 10 MHz was also done and output 3rd order intercept point (OIP3) of 49 dBm was obtained. (© 2008 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

Novel Carrier-Based PWM Methods for Multi-level Inverters

Carrier-based methods have been used widely for the switching of multilevel inverters due to their simplicity, flexibility and reduced computational requirements compared to Space Vector Modulation (SVM). Several multi-carrier modulation methods with miscellaneous properties have been already known. The paper proposes three novel multi-carrier techniques being more efficient for high-power inverter applications. While evaluating and comparing these new with all classical methods through measures like THD, WTHD, WTHD0, switching losses and DC bus utilization, the paper shows their advantges for applications of Diode-clamped and Cascade multi-level topologies by simulation results. The validity of obtained results is approved by experimental results.

Cascaded Diophantine Frequency Synthesis

Cascaded diophantine frequency synthesis (CDFS) is an approach to high-resolution frequency synthesis based on the mathematical properties of integer numbers and diophantine equations. CDFS can be implemented using two or more phase-locked loops (PLLs) and frequency mixing stages in a cascade topology. CDFS achieves frequency resolution arbitrarily finer than that of the constituent PLLs while maintaining their loop bandwidths and frequency hopping agility. CDFS results in intermediate signals with minimal frequency ranges in all frequency mixing stages, allowing for improved spectral purity and lower design complexity compared to the parallel form of its predecessor, diophantine frequency synthesis (DFS). CDFS architectures are modularly structured and expandable. The paper introduces CDFS focusing on the mathematical and algorithmic aspects.

Performance comparison of high-order IFLF and cascade analogue integrated lowpass filters

The magnitude and delay performance of integrated continuous-time gm–C lowpass filters is discussed. The analysis is based on tenth-order filters with equiripple group delay, implemented in CMOS fully differential form as inverse-follow-the-leader feedback (IFLF) and cascade topologies. A very-high-frequency operational transconductance amplifier (OTA) is used as the basic building block. The sensitivity performance is assessed by simulating IFLF and cascade filters with 27 real CMOS models released from MOSIS. Experimental and simulation results show that the passband magnitude sensitivity of the cascade filter is larger than that of the IFLF filter. In the stopband, the opposite is true. The results demonstrate that the group delay performance, on the other hand, is worse in the IFLF filter than in the cascade filter.

A 3.3-V, 15-bit, delta-sigma ADC with a signal bandwidth of 1.1 MHz for ADSL applications

The design of a high-resolution, high-speed, delta-sigma analog to-digital converter that operates from a single 3.3-V supply is presented. This supply voltage presents several design problems, such as reduced signal swing and nonzero switch resistance in the switched-capacitor circuits. These problems are tackled in this design by a careful optimization at the system level and by a detailed analysis of several circuit nonidealities. The converter uses a 2-1-1 cascade topology with optimized coefficients. For an oversampling-ratio of only 24, the converter achieves a signal-to-noise ratio of 87 dB, a signal-to-(noise+distortion) ratio of 82 dB, and an input dynamic range of 15 bits after comb filtering. The converter is sampled at 52.8 MHz, which results in the required signal bandwidth for asymmetrical digital subscriber line applications of 1.1 MHz. It is implemented in a 0.5-/spl mu/m CMOS technology, in a 5-mm/sup 2/ die area, and consumes 200 mW from a 3.3-V power supply.

Complex-signal sigma-delta modulators for quadrature bandpass A/D conversion

This paper presents a study on complex-signal sigma-delta (ΣΔ) modulators suitable for quadrature bandpass analogue-to-digital conversion of signals in monolithic radio receivers. The noise-shaping in complex-signal modulators is not symmetric with respect to dc, i.e. the zeros in the noise transfer function are not complex-conjugate as in conventional bandpass modulators. First-order ( L = 1), second-order ( L = 2) and high-order ( L > 2) cascade topologies are discussed together with design methodologies suitable for switched-capacitor (SC) realization. Complex-signal fully-differential SC integrators and sigma-delta modulators are also addressed. The concepts, design methodologies and circuits proposed have been validated through simulations made with TOSCA (V. Literali et al., IEEE Trans. CAD Integrated CAS, 12(9) (1993) 1376–1386) and SWITCAP-2 (K. Suyams et al., IEEE J. Solid-State Circuits, 25(6) (1990) 1403–1413).