Carry Propagation Chain Research Articles

A Timing-Aware Configurable Adder Based on Timing Detection for Low-Voltage Computing

Low-voltage computing effectively saves energy in circuit operations, but it suffers from an increasing propagation delay. Approximate computing can significantly reduce the propagation delay by using a simplified or improved circuit, albeit with an inevitable accuracy loss. To address these challenges, a timing-aware configurable adder (TACA) is proposed to achieve a good trade-off between energy efficiency and accuracy at low operating voltages. This design relies on the functions of timing-error detection and correction (TEDC) for the newly-proposed accuracy-configurable full adders (ACFAs). The ACFA operates in an exact mode and two approximate modes by using four transistors as power gating. The TEDC generates timing-error signals when the delay violates the timing constraint due to voltage overscaling. Then, an improved configuration scheme is developed to enable the ACFA to work in an approximate mode by allowing for error signals at runtime. This approximation shortens the carry propagation chain. Thus, the TACA is adapted to timing conditions at different supply voltages by reducing the propagation delay rather than the operation frequency.

Teaching redundant residue number system for electronics and computer students

This paper describes a study for teaching number system in a computer arithmetic course and addresses the existing gap in the current course by focusing on the characteristics of applications. A redundant residue number system (RRNS) is an efficient and innovative number system that inherits the interesting properties of both residue number system (RNS) and redundant number systems. It breaks the operands into residues by considering a moduli-set and then signifies the residues by a redundant representation. So, by limiting the carry propagation chain inside and outside the moduli, RRNS proposes more efficient arithmetic units which could be employed in digital signal processing (DSP) applications. Despite the applicability of RRNS, there is not well-organized teaching on RRNS covering the recent achievements. Besides, there is an important question for students and researchers what is the most appropriate number representation for each application category? In this paper, we present a step-by-step education process for RRNS that includes basic concepts of RNS and the redundant number system. Then we address characteristics of different applications that RRNS is suitable to be employed for them. So, the method gives a well-organized proceeding to computer arithmetic designers and students.

Design of Approximate Circuits by Fabrication of False Timing Paths: The Carry Cut-Back Adder

This paper introduces a novel method for designing approximate circuits by fabricating and exploiting false timing paths, i.e., critical paths that cannot be logically activated. This allows to strongly relax timing constraints while guaranteeing minimal and controlled behavioral change. This technique is applied to an approximate adder architecture, called the Carry Cut-Back Adder (CCBA), in which high-significance stages can cut the carry propagation chain at lower-significance positions. This lightweight approach prevents the logic activation of the carry chain, improving performance and energy efficiency while guaranteeing low worst-case errors. A design methodology is presented along with implementation, error optimization, and design-space minimization. The CCBA is proven capable of extremely high accuracy while displaying significant circuit savings. For a worst case precision of 99.999%, energy savings up to 36% are demonstrated compared with exact adders. Finally, an industry-oriented comparison of 32-bit approximate and truncated adders is carried out for mean and worst-case relative errors. The CCBA outperforms both state-of-the-art and truncated adders for high-accuracy and low-power circuits, confirming the interest of the proposed concept to help building highly-efficient approximate or precision-scalable hardware accelerators.

Area-Time-Power Efficient Maximally Redundant Signed-Digit Modulo 2n − 1 Adder and Multiplier

By increasing the length of input operands, standard binary number representation cannot satisfy the need for area-time-power efficient systems due to carry propagation chain problem. Redundant residue number system (RRNS) would be an appropriate solution to this demand as it divides large numbers to smaller ones on which the arithmetic operations could be performed in parallel. Maximally redundant signed-digit RNS (MRSD-RNS) has been recently presented as a low-power RRNS because the addition unit based on this number system consumes the least power among the existing RRNS encodings. In this work, a low-power MRSD-RNS multiplier for modulo 2n− 1 is proposed for the first time. The implementation results based on the TSMC-90 nm CMOS Technology indicate that our proposed design outperforms power, area, power-delay-product and area-delay-product in comparison with the efficient existing RRNS multipliers for the cases in which delay is not a limiting factor. It has also the least delay among the existing high-radix RRNS multipliers. Therefore, the proposed multiplier can meet the strict area-time-energy constraints which can be used as the core of signal processor in many applications.

CNTFET-based design of multi-bit adder circuits

ABSTRACTThis paper presents a novel design of a high performance full adder cell based on carbon nanotube field-effect transistors (CNTFET). This full adder cell has been designed to be used in ripple carry adder (RCA) optimally so that carry-propagation delay decreases without increase in hardware costs. High speed in RCA structure, the low number of transistors and simplicity in design are the main advantages of the proposed design in comparison with the previous works. Moreover, to increase the proposed RCA speed, carry-propagation chain has been reduced to six cells using only 14 transistors per 4 bits in the worst case, regardless of the adder width. The simulation results using HSPICE demonstrate that a significant improvement in delay, power and power-delay product compared with the state-of-the-art works can be achieved. The results in different temperatures, supply voltages, frequencies and load capacitors have also been obtained.

Efficient Low-Cost Fault-Localization and Self-Repairing Radix-2 Signed-Digit Adders Applying the Self-Dual Concept

Signed-digit adder, which eliminates carry propagation chain, can execute addition operation independent of the length of operands, in constant time. The confined carry propagation implies remarkable advantage in terms of error detection, localization, and correction. We developed a new low-cost technique, for fault-localization and error-correction, which utilizes the self-dual concept in binary signed-digit adders. The foundational idea of our technique is that the designed method, when fed by the complement of its functional input under the existence of a stuck-at fault, yields a fault-free inverse of the expected output. In this method, after detection of a fault, the method continues with input inversion, recomputation, and desired output inversion. The faulty component will localize by comparison of the faulty and fault-free outputs. Higher reliability with less computational time and reduced hardware-area overhead are the distinct features of this new design. In this method, all of the single stuck-at faults can be localized and corrected, whereas previous approaches were unable to localize and correct with 100 % reliability even with longer time durations and greater hardware cost. The experimental results prove that our design requires 20 %–90 % less time and 20 %–40 % smaller area overhead compared with a previous related work.

A novel reversible carry-selected adder with low latency

ABSTRACTReversible logic is getting more and more attention in quantum computing, optical computing, nanotechnology and low-power complementary metal oxide semiconductor designs since reversible circuits do not loose information during computation and have only small energy dissipation. In this paper, a novel carry-selected reversible adder is proposed primarily optimised for low latency. A 4-bit reversible full adder with two kinds of outputs, minimum delay and optimal quantum cost is presented as the building block for -bit reversible adder. Three new reversible gates NPG (new Peres gate), TEPG (triple extension of Peres gate) and RMUX21 (reversible 2-to-1 multiplexer) are proposed and utilised to design efficient adder units. The secondary carry propagation chain is carefully designed to reduce the time consumption. The novelty of the proposed design is the consideration of low latency. The comparative study shows that the proposed adder achieves the improvement from 61.46% to 95.29% in delay over the existing designs.

IMPLEMENTATION OF HIGH SPEED-LOW POWER TRUNCATION ERROR TOLERANT ADDER

Now a Days in modern VLSI technology different kinds of errors are invitable. A new type of adder i.e. error tolerant adder(ETA) is proposed to tolerate those errors and to attain low power consumption and high speed performance in DSP systems. In conventional adder circuit, delay is mainly certified to the carry propagation chain along the critical path, from the LSB to MSB. If the carry propagation can be eliminated by the technique proposed in this paper, a great improvement in speed performance and power consumption is achieved. By operating shifting and addition in parallel, the error tolerant adder tree compensates for the truncation errors. To prove the feasibility of the ETA, normal addition operation present in the DFT or DCT algorithm is replaced by the proposed addition arithmetic and the experimental results are shown. In this paper we propose error tolerant Adder (ETA). In the view of DSP applications the ETA is able to case the strict restriction on accuracy, speed performance and power consumption when compared to the conventional Adders, the proposed one provides 76% improvement in power-delay product such a ETA plays a key role in digital signal processing system that can tolerate certain amount of errors.

A low energy dual-mode adder

VLSI designs are typically data-independent and as such, they must produce the correct result even for the worst-case inputs. Adders in particular assume that addition must be completed within prescribed number of clock cycles, independently of the operands. While the longest carry propagation of an n-bit adder is n bits, its expected length is only O(log2n) bits. We present a novel dual-mode adder architecture that reduces the average energy consumption in up to 50%. In normal mode the adder targets the O(log2n)-bit average worst-case carry propagation chains, while in extended mode it accommodates the less frequent O(n)-bit chain. We prove that minimum energy is achieved when the adder is designed for O(log2n) carry propagation, and present a circuit implementation. Dual-mode adders enable voltage scaling of the entire system, potentially supporting further overall energy reduction. The energy-time tradeoff obtained when incorporating such adders in ordinary microprocessor’s pipeline and other architectures is discussed.

Carry propagation in multiplication by constants

Suppose that a random n -bit number V is multiplied by an odd constant M ≥ 3, by adding shifted versions of the number V corresponding to the 1s in the binary representation of the constant M . Suppose further that the additions are performed by carry-save adders until the number of summands is reduced to two, at which time the final addition is performed by a carry-propagate adder. We show that in this situation the distribution of the length of the longest carry-propagation chain in the final addition is the same (up to terms tending to 0 as n → ∞) as when two independent n -bit numbers are added, and in particular the mean and variance are the same (again up to terms tending to 0). This result applies to all possible orders of performing the carry-save additions.

Design of a multiple‐operand redundant binary adder

AbstractThis paper describes a novel multiple‐operand redundant binary adder. The novel multiple‐operand addition algorithm can eliminate the carry propagation chain by dividing the input operands into an even place part and an odd place part, and adding them. The multiple‐operand adder with this algorithm can add six operands in parallel, and is faster than the ordinary tree‐structured method. A hardware model for the proposed adder implemented by the bidirectional current‐mode MOSFET circuit technology is described. Simulations have been made with HSPICE in order to verify the function of the proposed circuit. © 2002 Wiley Periodicals, Inc. Syst Comp Jpn, 33(10): 1–9, 2002; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/scj.10182

Design and analysis of asynchronous adders

An asynchronous adder can take advantage of the shorter carry propagation chains that occur in practice and exhibit a data-dependent computation delay. Basically, an asynchronous adder has a mechanism to announce early completion by detecting when it is done. Such an adder is extremely useful in asynchronous implementation of computing structures. In this paper we evaluate the designs tradeoffs of well-known asynchronous adder configurations based on ripple-carry and carry lookahead topologies. We show that, using complex gates, carry lookahead asynchronous adders can be realised that outperform ripple-carry asynchronous adders, both in average-case delay and worst-case delay without increasing the area and power consumption. The underlying timing assumptions and applications of the adder in asynchronous pipelines (micropipelines) are also discussed.

Hybrid signed-digit number systems: a unified framework for redundant number representations with bounded carry propagation chains

A novel hybrid number representation is proposed. It includes the two's complement representation and the signed-digit representation as special cases. The hybrid number representations proposed are capable of bounding the maximum length of carry propagation chains during addition to any desired value between 1 and the entire word length. The framework reveals a continuum of number representations between the two extremes of two's complement and signed-digit number systems and allows a unified performance analysis of the entire spectrum of implementations of adders, multipliers and alike. We present several static CMOS implementations of a two-operand adder which employ the proposed representations. We then derive quantitative estimates of area (in terms of the required number of transistors) and the maximum carry propagation delay for such an adder. The analysis clearly illustrates the trade-offs between area and execution time associated with each of the possible representations. We also discuss adder trees for parallel multipliers and show that the proposed representations lead to compact adder trees with fast execution times. In practice, the area available to a designer is often limited. In such cases, the designer can select the particular hybrid representation that yields the most suitable implementation (fastest, lowest power consumption, etc.) while satisfying the area constraint. Similarly, if the worst case delay is predetermined, the designer can select a hybrid representation that minimizes area or power under the delay constraint.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A novel Josephson adder without carry propagation delay

The authors describe a novel Josephson adder based on the radix-2 signed-digit number representation. In the proposed adder, the addition operation can be carried out in a constant time independent of word length owing to the elimination of the carry propagation chain. A critical path for generating the sum signal can be completed through only three series gates. A carry signal and an intermediate sum signal for all digits in the adder are simultaneously generated in the first step, and the final sum signal is obtained in the second step. Features of the proposed adder are a simple construction, ultra-high speed, and low power consumption. The principle of constructing the adder with an 8 b word length using superconducting quantum interference devices (SQUIDs) is described in detail, and simulation results are presented. Results show that reliable operation can be achieved for the longest delay time of 120 ps for the 8 b adder.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

High-speed multiplier for digital signal processing

A high-speed optical system capable of performing <i>n</i>-bit multiplication in a time proportional to log₂<i>n</i> is presented. The simultaneous generation and the optical regrouping of all the partial products and the pairwise addition of the partial products by means of a binary tree of adders capable of adding any two numbers in a single stage (by completely eliminating the carry propagation chain) are unique features of this multiplier. The input data to the multiplier can be in either a binary or a modified signed digit number system. The simultaneous generation and the pairwise addition of the partial products are accomplished by means of the principle of symbolic substitution logic that was originally proposed by Brenner.

Single-stage optical adder/subtractor

Fully parallel processors call for a technology that is inherently parallel, a suitable number system, and an efficient encoding scheme for handling the data. The throughput of a binary adder/subtractor is limited by the carry propagation to the most significant bits. Optical adders using a modified signed digit (MSD) number system have been proposed to eliminate the carry propagation chain encountered in binary adders. The MSD number system satisfies the requirements of fully parallel addition/ subtraction by limiting the carry propagation to two positions to the left. This enables one to carry out the addition/subtraction of two <i>n</i>-digit MSD numbers in three stages, independent of <i>n</i>. In this paper it is shown that by suitably exploiting the redundant nature of the MSD number system, the carry generation and propagation can be completely eliminated. The MSD adder/subtractor presented in this paper fully exploits the redundant nature of the MSD number system and performs the addition/subtraction of two numbers in a single stage. The adder employs 81 substitution rules to perform the addition/subtraction of two MSD numbers in a single stage. The number of substitution rules can be reduced to 16 if the input numbers are limited to binary. The proposed architecture reduces the computation time by 33.3% compared to the three-stage MSD adder originally proposed.

High-speed signed digital multipiers for VLSI

High-speed multipliers are essential building blocks for modern computers, signal processing and other digital systems. A new parallel multiplier configuration is developed in this paper by using the signed digital number systems incorporated with the modified version of Booth's algorithm. The carry propagation chain has been broken in Add/ Subtract operations. Thus it can perform N × N bit multiplication in parallel with a time proportional to log 2( N 2 ) . It is almost double the speed of Wallace tree for which its computing time is proportional to log 2 N. The number of computing cells is proportional to n·log 2( n/2) which is less than that of the conventional multiplier. A regular array structure for this scheme is suitable for VLSI implementation.

A fast inner product processor based on equal alignments

Inner product computation is an important operation, invoked repeatedly in matrix multiplications. A high-speed inner product processor can be very useful (among many possible applications) in real-time signal processing. This paper presents the design of a fast inner product processor, with appreciably reduced latency and cost. The inner product processor is implemented with a tree of carry-propagate or carry-save adders; this structure is obtained with the incorporation of three innovations in the conventional multiply/add tree: (1) The leaf-multipliers are expanded into adder subtrees, thus achieving an O(log Nb) latency, where N denotes the number of elements in a vector and b the number of bits in each element. (2) The partial products, to be summed in producing an inner product, are reordered according to their “minimum alignments.” This reordering brings approximately a 20% saving in hardware—including adders and data paths. The reduction in adder widths also yields savings in carry propagation time for carry-propagate adders. (3) For trees implemented with carry-save adders, the partial product reordering also serves to truncate the carry propagation chain in the final propagation stage by 2 log b − 1 positions, thus significantly reducing the latency further. A form of the Baugh and Wooley algorithm is adopted to implement two's complement notation with changes only in peripheral hardware.

Signed-Digit Numbe Representations for Fast Parallel Arithmetic

This paper describes a class of number representations which are called signed-digit representations. Signed-digit representations limit carry-propagation to one position to the left during the operations of addition and subtraction in digital computers. Carry-propagation chains are eliminated by the use of redundant representations for the operands. Redundancy in the number representation allows a method of fast addition and subtraction in which each sum (or difference) digit is the function only of the digits in two adjacent digital positions of the operands. The addition time for signed-digit numbers of any length is equal to the addition time for two digits. The paper discusses the properties of signed-digit representations and arithmetic operations with signed-digit numbers: addition, subtraction, multiplication, division and roundoff. A brief discussion of logical design problems for a signed-digit adder concludes the presentation.